Academic and industry research progress in germanium nanodevices

Abstract: The scaling of complementary metal oxide semiconductor (CMOS) transistors has led to the silicon dioxide layer used as a gate dielectric becoming so thin that the gate leakage current becomes too large. This led to the replacement of SiO2 by a physically thicker layer of a higher dielectric constant or ‘high-K’ oxide such as hafnium oxide. Intensive research was carried out to develop these oxides into high quality electronic materials. In addition, the incorporation of Ge in the CMOS transistor structure has been employed to enable higher carrier mobility and performance. This review covers both scientific and technological issues related to the high-K gate stack – the choice of oxides, their deposition, their structural and metallurgical behaviour, atomic diffusion, interface structure, their electronic structure, band offsets, electronic defects, charge trapping and conduction mechanisms, reliability, mobility degradation and oxygen scavenging to achieve the thinnest oxide thicknesses. The high K oxides were implemented in conjunction with a replacement of polycrystalline Si gate electrodes with metal gates. The strong metallurgical interactions between the gate electrodes and the HfO2 which resulted an unstable gate threshold voltage resulted in the use of the lower temperature ‘gate last’ process flow, in addition to the standard ‘gate first’ approach. Work function control by metal gate electrodes and by oxide dipole layers is discussed. The problems associated with high K oxides on Ge channels are also discussed.

Abstract: In the past five decades, the semiconductor industry has gone through two distinct eras of scaling: the geometric (or classical) scaling era and the equivalent (or effective) scaling era. As transistor and memory features approach 10 nanometres, it is apparent that room for further scaling in the horizontal direction is running out. In addition, the rise of data abundant computing is exacerbating the interconnect bottleneck that exists in conventional computing architecture between the compute cores and the memory blocks. Here we argue that electronics is poised to enter a new, third era of scaling — hyper-scaling — in which resources are added when needed to meet the demands of data abundant workloads. This era will be driven by advances in beyond-Boltzmann transistors, embedded non-volatile memories, monolithic three-dimensional integration and heterogeneous integration techniques. This Perspective argues that electronics is poised to enter a new era of scaling – hyper-scaling – driven by advances in beyond-Boltzmann transistors, embedded non-volatile memories, monolithic three-dimensional integration, and heterogeneous integration techniques.

Abstract: Tetragonal CsPb2Br5 nanosheets were obtained by an oriented attachment of orthorhombic CsPbBr3 nanocubes, involving a lateral shape evolution from octagonal to square. Meanwhile, the experimental results, together with DFT simulation results, indicated that the tetragonal CsPb2Br5 is an indirect bandgap semiconductor that is PL-inactive with a bandgap of 2.979 eV.

Abstract: In this review article, we address key material parameters as well as the fabrication and application of crystalline GeSn binary and SiGeSn ternary alloys. Here, the transition from an indirect to a fundamental direct bandgap material will be discussed. The main emphasis, however, is put on the Si–Ge–Sn epitaxy. The low solid solubility of α-Sn in Ge and Si of below 1 at.% along with the large lattice mismatch between α-Sn (6.489 A) and Ge (5.646 A) or Si (5.431 A) of about 15% and 20%, respectively, requires non-equilibrium growth processes. The most commonly used approaches, i.e. molecular beam epitaxy (MBE) and chemical vapor deposition (CVD), will be reviewed in terms of crucial process parameters, structural as well as optical quality and employed precursor combinations including Germanium hydrides, Silicon hydrides and a variety of Sn compounds like SnD4, SnCl4 or C6H5SnD3. Special attention is devoted to the growth temperature window and growth rates being the most important growth parameters concerning the substitutional incorporation of Sn atoms into the Ge diamond lattice. Furthermore, the mainly CVD-driven epitaxy of high quality SiGeSn ternary alloys, allowing the decoupling of band engineering and lattice constant, is presented. Since achieving fundamental direct bandgap Sn-based materials strongly depends on the applied strain within the epilayers, ways to control and modify the strain are shown, especially the plastic strain relaxation of (Si)GeSn layers grown on Ge. Based on recently achieved improvements of the crystalline quality, novel low power and high mobility GeSn electronic and photonic devices have been developed and are reviewed in this paper. The use of GeSn as optically active gain or channel material with its lower and potentially direct bandgap compared to fundamentally indirect Ge (0.66 eV) and Si (1.12 eV) provides a viable solution to overcome the obstacles in both fields photonics and electronics. Moreover, the epitaxial growth of Sn-based semiconductors using CMOS compatible substrates on the road toward a monolithically integrated and efficient group IV light emitter is presented.

Abstract: Germanium nanoparticles have excited scientists and engineers because of their size-dependent optical properties and their potential applications in optoelectronics, biological imaging and therapeutics, flash memories, and lithium-ion batteries. In order to further develop these applications and to gain deeper insights into their size-dependent properties, robust and facile synthetic methods are needed to controllably synthesize Ge nanoparticles. However, when compared to other II–VI, IV–VI, and III–V semiconductor systems, colloidal routes to Ge NPs with uniform sizes and shapes are much less mature. In this Review Article, we highlight the progress that has been made in this field and provide insights into the strategies used for the colloidal synthesis of size and shape-controlled germanium nanomaterials. We also survey some of the potential applications of these materials in optoelectronics, biological imaging, and energy conversion and storage. Finally, we discuss the colloidal synthesis of other germanium-containing compounds, emphasizing technologically relevant germanium chalcogenides that include GeS, GeSe, and GeTe.

Abstract: A 45 nm logic technology is described that for the first time incorporates high-k + metal gate transistors in a high volume manufacturing process. The transistors feature 1.0 nm EOT high-k gate dielectric, dual band edge workfunction metal gates and third generation strained silicon, resulting in the highest drive currents yet reported for NMOS and PMOS. The technology also features trench contact based local routing, 9 layers of copper interconnect with low-k ILD, low cost 193 nm dry patterning, and 100% Pb-free packaging. Process yield, performance and reliability are demonstrated on 153 Mb SRAM arrays with SRAM cell size of 0.346 mum2, and on multiple microprocessors.

Abstract: This paper describes the details of a novel strained transistor architecture which is incorporated into a 90nm logic technology on 300mm wafers The unique strained PMOS transistor structure features an epitaxially grown strained SiGe film embedded in the source drain regions Dramatic performance enhancement relative to unstrained devices are reported These transistors have gate length of 45nm and 50nm for NMOS and PMOS respectively, 12nm physical gate oxide and Ni salicide World record PMOS drive currents of 700/spl mu/A//spl mu/m (high V/sub T/) and 800/spl mu/A//spl mu/m (low V/sub T/) at 12V are demonstrated NMOS devices exercise a highly tensile silicon nitride capping layer to induce tensile strain in the NMOS channel region High NMOS drive currents of 126mA//spl mu/m (high VT) and 145mA//spl mu/m (low VT) at 12V are reported The technology is mature and is being ramped into high volume manufacturing to fabricate next generation Pentium/spl reg/ and Intel/spl reg/ Centrino/spl trade/ processor families

Abstract: A method of controlling threading dislocation densities in Ge on Si involving graded SiGe layers and chemical-mechanical polishing (CMP) is presented. This method has allowed us to grow a relaxed graded buffer to 100% Ge without the increase in threading dislocation density normally observed in thick graded structures. This sample has been characterized by transmission electron microscopy, etch-pit density, atomic force microscopy, Nomarski optical microscopy, and triple-axis x-ray diffraction. Compared to other relaxed graded buffers in which CMP was not implemented, this sample exhibits improvements in threading dislocation density and surface roughness. We have also made process modifications in order to eliminate particles due to gas-phase nucleation and cracks due to thermal mismatch strain. We have achieved relaxed Ge on Si with a threading dislocation density of 2.1×106 cm−2, and we expect that further process refinements will lead to lower threading dislocation densities on the order of bulk Ge su...

Abstract: Recently developed high-permittivity (k) materials have reopened the door to Ge as a channel material in metal-oxide-semiconductor field-effect transistors (MOSFETs). High-k/Ge gate stacks are very promising for future nanoscale devices. This article reviews the opportunities and challenges of high-k/Ge MOSFET technology. The most important technical issue is the passivation of the Ge surface. Physical phenomena and electrical characteristics that depend on the high-k/Ge interface are discussed on the basis of the material properties of Ge oxide to provide insights for future progress.