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Journal ArticleDOI

Academic and industry research progress in germanium nanodevices

Ravi Pillarisetty1
17 Nov 2011-Nature (Nature Publishing Group)-Vol. 479, Iss: 7373, pp 324-328
TL;DR: Germanium-based transistors have the potential to operate at high speeds with low power requirements and might therefore be used in non-silicon-based semiconductor technology in the future.
Abstract: Silicon has enabled the rise of the semiconductor electronics industry, but it was not the first material used in such devices. During the 1950s, just after the birth of the transistor, solid-state devices were almost exclusively manufactured from germanium. Today, one of the key ways to improve transistor performance is to increase charge-carrier mobility within the device channel. Motivated by this, the solid-state device research community is returning to investigating the high-mobility material germanium. Germanium-based transistors have the potential to operate at high speeds with low power requirements and might therefore be used in non-silicon-based semiconductor technology in the future.
Citations
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Journal ArticleDOI
TL;DR: In this paper, the existing methods for cleaning the Ge(001) surface are reviewed and compared for the first time, and three broad categories of cleaning techniques have been successfully demonstrated to obtain a clean Ge surface.
Abstract: In recent years, research on Ge nanodevices has experienced a renaissance, as Ge is being considered a possible high mobility channel material replacement for Si MOSFET devices. However, for reliable high performance devices, an atomically flat and perfectly clean Ge surface is of utmost importance. In this review, the existing methods for cleaning the Ge(001) surface are reviewed and compared for the first time. The review discusses three broad categories of cleaning techniques that have been successfully demonstrated to obtain a clean Ge surface. First, the use of ultraviolet light and/or oxygen plasma is discussed. Both techniques remove carbon contamination from the Ge surface and simultaneously form an oxide passivation layer. Second, in situ ion sputtering in combination with germanium regrowth, which can lead to extremely clean and well-ordered Ge surfaces, is discussed. Finally, various wet-etching recipes are summarized, with focus on hydrofluoric acid (HF), NH4OH, and HCl. Despite the success of...

36 citations

Journal ArticleDOI
TL;DR: In this article, a two-dimensional hole gas of high mobility was demonstrated in a very shallow strained germanium channel, which is located only 22 nm below the surface, leading to mean free paths.
Abstract: Buried-channel semiconductor heterostructures are an archetype material platform to fabricate gated semiconductor quantum devices. Sharp confinement potential is obtained by positioning the channel near the surface, however nearby surface states degrade the electrical properties of the starting material. In this paper we demonstrate a two-dimensional hole gas of high mobility ($5\times 10^{5}$ cm$^2$/Vs) in a very shallow strained germanium channel, which is located only 22 nm below the surface. This high mobility leads to mean free paths $\approx6 \mu m$, setting new benchmarks for holes in shallow FET devices. Carriers are confined in an undoped Ge/SiGe heterostructure with reduced background contamination, sharp interfaces, and high uniformity. The top-gate of a dopant-less field effect transistor controls the carrier density in the channel. The high mobility, along with a percolation density of $1.2\times 10^{11}\text{ cm}^{-2}$, light effective mass (0.09 m$_e$), and high g-factor (up to $7$) highlight the potential of undoped Ge/SiGe as a low-disorder material platform for hybrid quantum technologies.

33 citations

Journal ArticleDOI
TL;DR: In this article, a fabrication of tunnel field effect transistors using InGaAs nanowire/Si heterojunctions and the characterization of scaling of channel lengths was reported. But the authors did not consider the channel length of the transistors.
Abstract: We report on a fabrication of tunnel field-effect transistors using InGaAs nanowire/Si heterojunctions and the characterization of scaling of channel lengths. The devices consisted of single InGaAs nanowires with a diameter of 30 nm grown on p-type Si(111) substrates. The switch demonstrated steep subthreshold-slope (30 mV/decade) at drain-source voltage (VDS) of 0.10 V. Also, pinch-off behavior appeared at moderately low VDS, below 0.10 V. Reducing the channel length of the transistors attained a steep subthreshold slope (<60 mV/decade) and enhanced the drain current, which was 100 higher than that of the longer channels.

33 citations

Journal ArticleDOI
TL;DR: In this paper, a review of very slow diffusion at the interfaces of heterostructures, discerning kinetics of intermetallic phase formation at interfaces in thin films and multilayers on annealing at relatively lower temperatures, was presented.

33 citations

Journal ArticleDOI
TL;DR: The Birmingham Parallel Genetic Algorithm has been adopted for the global optimization of free and MgO(100)-supported Pd, Au and AuPd nanocluster structures, over the size range N = 4-10 and shows a high degree of success.
Abstract: The Birmingham Parallel Genetic Algorithm (BPGA) has been adopted for the global optimization of free and MgO(100)-supported Pd, Au and AuPd nanocluster structures, over the size range N = 4–10. Structures were evaluated directly using density functional theory, which has allowed the identification of Pd, Au and AuPd global minima. The energetics, structures, and tendency of segregation have been evaluated by different stability criteria such as binding energy, excess energy, second difference in energy, and adsorption energy. The ability of the approach in searching for putative global minimum has been assessed against a systematic homotop search method, which shows a high degree of success.

33 citations

References
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Proceedings ArticleDOI
01 Dec 2007
TL;DR: In this paper, a 45 nm logic technology is described that for the first time incorporates high-k + metal gate transistors in a high volume manufacturing process, resulting in the highest drive currents yet reported for NMOS and PMOS.
Abstract: A 45 nm logic technology is described that for the first time incorporates high-k + metal gate transistors in a high volume manufacturing process. The transistors feature 1.0 nm EOT high-k gate dielectric, dual band edge workfunction metal gates and third generation strained silicon, resulting in the highest drive currents yet reported for NMOS and PMOS. The technology also features trench contact based local routing, 9 layers of copper interconnect with low-k ILD, low cost 193 nm dry patterning, and 100% Pb-free packaging. Process yield, performance and reliability are demonstrated on 153 Mb SRAM arrays with SRAM cell size of 0.346 mum2, and on multiple microprocessors.

973 citations

Proceedings ArticleDOI
08 Dec 2003
TL;DR: In this article, the authors describe a novel strained transistor architecture which is incorporated into a 90nm logic technology on 300mm wafers, which features an epitaxially grown strained SiGe film embedded in the source drain regions.
Abstract: This paper describes the details of a novel strained transistor architecture which is incorporated into a 90nm logic technology on 300mm wafers The unique strained PMOS transistor structure features an epitaxially grown strained SiGe film embedded in the source drain regions Dramatic performance enhancement relative to unstrained devices are reported These transistors have gate length of 45nm and 50nm for NMOS and PMOS respectively, 12nm physical gate oxide and Ni salicide World record PMOS drive currents of 700/spl mu/A//spl mu/m (high V/sub T/) and 800/spl mu/A//spl mu/m (low V/sub T/) at 12V are demonstrated NMOS devices exercise a highly tensile silicon nitride capping layer to induce tensile strain in the NMOS channel region High NMOS drive currents of 126mA//spl mu/m (high VT) and 145mA//spl mu/m (low VT) at 12V are reported The technology is mature and is being ramped into high volume manufacturing to fabricate next generation Pentium/spl reg/ and Intel/spl reg/ Centrino/spl trade/ processor families

729 citations

Journal ArticleDOI
TL;DR: In this paper, a method of controlling threading dislocation densities in Ge on Si involving graded SiGe layers and chemical-mechanical polishing (CMP) is presented.
Abstract: A method of controlling threading dislocation densities in Ge on Si involving graded SiGe layers and chemical-mechanical polishing (CMP) is presented. This method has allowed us to grow a relaxed graded buffer to 100% Ge without the increase in threading dislocation density normally observed in thick graded structures. This sample has been characterized by transmission electron microscopy, etch-pit density, atomic force microscopy, Nomarski optical microscopy, and triple-axis x-ray diffraction. Compared to other relaxed graded buffers in which CMP was not implemented, this sample exhibits improvements in threading dislocation density and surface roughness. We have also made process modifications in order to eliminate particles due to gas-phase nucleation and cracks due to thermal mismatch strain. We have achieved relaxed Ge on Si with a threading dislocation density of 2.1×106 cm−2, and we expect that further process refinements will lead to lower threading dislocation densities on the order of bulk Ge su...

620 citations

Journal ArticleDOI
Yoshiki Kamata1
TL;DR: In this article, the opportunities and challenges of high-k/Ge MOSFETs are discussed on the basis of the material properties of Ge oxide to provide insights for future progress.

443 citations