Academic and industry research progress in germanium nanodevices
TL;DR: Germanium-based transistors have the potential to operate at high speeds with low power requirements and might therefore be used in non-silicon-based semiconductor technology in the future.
Abstract: Silicon has enabled the rise of the semiconductor electronics industry, but it was not the first material used in such devices. During the 1950s, just after the birth of the transistor, solid-state devices were almost exclusively manufactured from germanium. Today, one of the key ways to improve transistor performance is to increase charge-carrier mobility within the device channel. Motivated by this, the solid-state device research community is returning to investigating the high-mobility material germanium. Germanium-based transistors have the potential to operate at high speeds with low power requirements and might therefore be used in non-silicon-based semiconductor technology in the future.
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TL;DR: In this article, the authors studied the relationship between the electrical properties of polycrystalline Ge and its TFT performance using high-mobility Ge formed on glass using their recently developed solid-phase crystallization technique.
Abstract: Low-temperature formation of Ge thin-film transistors (TFTs) on insulators has been widely investigated to improve the performance of Si large-scale integrated circuits and mobile terminals. Here, we studied the relationship between the electrical properties of polycrystalline Ge and its TFT performance using high-mobility Ge formed on glass using our recently developed solid-phase crystallization technique. The field-effect mobility μFE and on/off currents of the accumulation-mode TFTs directly reflected the Hall hole mobility μHall, hole concentration, and film thickness of Ge. By thinning the 100-nm thick Ge layer with a large grain size (3.7 μm), we achieved a high μHall (190 cm2/Vs) in a 55-nm thick film that was almost thin enough to fully deplete the channel. The TFT using this Ge layer exhibited both high μFE (170 cm2/Vs) and on/off current ratios (∼102). This is the highest μFE among low-temperature (<500 °C) polycrystalline Ge TFTs without minimizing the channel region (<1 μm).
22 citations
TL;DR: In this paper, a quantitative dependence of the Sb segregation ratio in Ge(001) films grown by molecular beam epitaxy was revealed experimentally and modeled theoretically taking into account both the terrace-mediated and step-edge-mediated segregation mechanisms.
Abstract: Antimony segregation in Ge(001) films grown by molecular beam epitaxy was studied. A quantitative dependence of the Sb segregation ratio in Ge on growth temperature was revealed experimentally and modeled theoretically taking into account both the terrace-mediated and step-edge-mediated segregation mechanisms. A nearly 5-orders-of-magnitude increase in the Sb segregation ratio in a relatively small temperature range of 180–350 °C was obtained, which allowed to form Ge:Sb doped layers with abrupt boundaries and high crystalline quality using the temperature switching method that was proposed earlier for Si-based structures. This technique was employed for fabrication of different kinds of n-type Ge structures which can be useful for practical applications like heavily doped n+-Ge films or δ-doped layers. Estimation of the doping profiles sharpness yielded the values of 2–5 nm per decade for the concentration gradient at the leading edge and 2–3 nm for the full-width-half-maximum of the Ge:Sb δ-layers. Electrical characterization of grown Ge:Sb structures revealed nearly full electrical activation of Sb atoms and the two-dimensional nature of charge carrier transport in δ-layers.
21 citations
TL;DR: In this paper, the hole mobility of the solid-phase-crystallized Ge layer is significantly improved by controlling the deposition temperature of Ge (50?200?C) and the Ge thickness (50?500 nm) and by applying post annealing at 500?C.
Abstract: The hole mobility of the solid-phase-crystallized Ge layer is significantly improved by controlling the deposition temperature of Ge (50?200 ?C) and the Ge thickness (50?500 nm) and by applying post annealing at 500 ?C. The resulting hole mobility ? 450 cm2 V?1 s?1 ? is the highest reported value to date among semiconductor layers directly formed on glass. The mechanism of the mobility enhancement is discussed from the perspective of three carrier scattering factors: grain boundary scattering, interface scattering, and impurity scattering. The high-hole mobility Ge layer formed via the simple fabrication process is useful for high-speed thin-film transistors.
21 citations
TL;DR: It is found that As doping into amorphous Ge significantly influenced the subsequent solid-phase crystallization and the low-temperature synthesis of high-mobility Ge on insulators will provide a pathway for the monolithic integration ofhigh-performance Ge-CMOS onto Si-LSIs and flat-panel displays.
Abstract: High-electron-mobility polycrystalline Ge (poly-Ge) thin films are difficult to form because of their poor crystallinity, defect-induced acceptors and low solid solubility of n-type dopants. Here, we found that As doping into amorphous Ge significantly influenced the subsequent solid-phase crystallization. Although excessive As doping degraded the crystallinity of the poly-Ge, the appropriate amount of As (~1020 cm−3) promoted lateral growth and increased the Ge grain size to approximately 20 μm at a growth temperature of 375 °C. Moreover, neutral As atoms in poly-Ge reduced the trap-state density and energy barrier height of the grain boundaries. These properties reduced grain boundary scattering and allowed for an electron mobility of 370 cm2/Vs at an electron concentration of 5 × 1018 cm−3 after post annealing at 500 °C. The electron mobility further exceeds that of any other n-type poly-Ge layers and even that of single-crystal Si wafers with n ≥ 1018 cm−3. The low-temperature synthesis of high-mobility Ge on insulators will provide a pathway for the monolithic integration of high-performance Ge-CMOS onto Si-LSIs and flat-panel displays.
21 citations
TL;DR: A combined scanning tunneling microscopy, secondary ions mass spectrometry, and magnetotransport study is presented to understand the atomistic doping process of Ge by P2 molecules to achieve controlled high n-type doping.
Abstract: The achievement of controlled high n-type doping in Ge will enable the fabrication of a number of innovative nanoelectronic and photonic devices. In this work, we present a combined scanning tunnel...
21 citations
References
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01 Dec 2007
TL;DR: In this paper, a 45 nm logic technology is described that for the first time incorporates high-k + metal gate transistors in a high volume manufacturing process, resulting in the highest drive currents yet reported for NMOS and PMOS.
Abstract: A 45 nm logic technology is described that for the first time incorporates high-k + metal gate transistors in a high volume manufacturing process. The transistors feature 1.0 nm EOT high-k gate dielectric, dual band edge workfunction metal gates and third generation strained silicon, resulting in the highest drive currents yet reported for NMOS and PMOS. The technology also features trench contact based local routing, 9 layers of copper interconnect with low-k ILD, low cost 193 nm dry patterning, and 100% Pb-free packaging. Process yield, performance and reliability are demonstrated on 153 Mb SRAM arrays with SRAM cell size of 0.346 mum2, and on multiple microprocessors.
973 citations
08 Dec 2003
TL;DR: In this article, the authors describe a novel strained transistor architecture which is incorporated into a 90nm logic technology on 300mm wafers, which features an epitaxially grown strained SiGe film embedded in the source drain regions.
Abstract: This paper describes the details of a novel strained transistor architecture which is incorporated into a 90nm logic technology on 300mm wafers The unique strained PMOS transistor structure features an epitaxially grown strained SiGe film embedded in the source drain regions Dramatic performance enhancement relative to unstrained devices are reported These transistors have gate length of 45nm and 50nm for NMOS and PMOS respectively, 12nm physical gate oxide and Ni salicide World record PMOS drive currents of 700/spl mu/A//spl mu/m (high V/sub T/) and 800/spl mu/A//spl mu/m (low V/sub T/) at 12V are demonstrated NMOS devices exercise a highly tensile silicon nitride capping layer to induce tensile strain in the NMOS channel region High NMOS drive currents of 126mA//spl mu/m (high VT) and 145mA//spl mu/m (low VT) at 12V are reported The technology is mature and is being ramped into high volume manufacturing to fabricate next generation Pentium/spl reg/ and Intel/spl reg/ Centrino/spl trade/ processor families
729 citations
TL;DR: In this paper, a method of controlling threading dislocation densities in Ge on Si involving graded SiGe layers and chemical-mechanical polishing (CMP) is presented.
Abstract: A method of controlling threading dislocation densities in Ge on Si involving graded SiGe layers and chemical-mechanical polishing (CMP) is presented. This method has allowed us to grow a relaxed graded buffer to 100% Ge without the increase in threading dislocation density normally observed in thick graded structures. This sample has been characterized by transmission electron microscopy, etch-pit density, atomic force microscopy, Nomarski optical microscopy, and triple-axis x-ray diffraction. Compared to other relaxed graded buffers in which CMP was not implemented, this sample exhibits improvements in threading dislocation density and surface roughness. We have also made process modifications in order to eliminate particles due to gas-phase nucleation and cracks due to thermal mismatch strain. We have achieved relaxed Ge on Si with a threading dislocation density of 2.1×106 cm−2, and we expect that further process refinements will lead to lower threading dislocation densities on the order of bulk Ge su...
620 citations
TL;DR: In this article, the opportunities and challenges of high-k/Ge MOSFETs are discussed on the basis of the material properties of Ge oxide to provide insights for future progress.
443 citations