Academic and industry research progress in germanium nanodevices
TL;DR: Germanium-based transistors have the potential to operate at high speeds with low power requirements and might therefore be used in non-silicon-based semiconductor technology in the future.
Abstract: Silicon has enabled the rise of the semiconductor electronics industry, but it was not the first material used in such devices. During the 1950s, just after the birth of the transistor, solid-state devices were almost exclusively manufactured from germanium. Today, one of the key ways to improve transistor performance is to increase charge-carrier mobility within the device channel. Motivated by this, the solid-state device research community is returning to investigating the high-mobility material germanium. Germanium-based transistors have the potential to operate at high speeds with low power requirements and might therefore be used in non-silicon-based semiconductor technology in the future.
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TL;DR: Germanium nanocrystals (Ge NCs) have attracted increasing attention as a promising alternative to II-VI and IV-VI semiconductor materials as they are cheap, "green," electrochemically stable, and compatible with existing CMOS processing methods as discussed by the authors.
Abstract: Germanium nanocrystals (Ge NCs) have attracted increasing attention as a promising alternative to II-VI and IV-VI semiconductor materials as they are cheap, "green," electrochemically stable, and compatible with existing CMOS processing methods. Germanium is a particularly attractive material for optoelectronic applications as it combines a narrow band gap with high carrier mobilities and a large exciton Bohr radius. Solution-phase synthesis and characterisation of size monodisperse alkyl-terminated Ge NCs are demonstrated. Ge NCs were synthesised under inert atmospheric conditions via the reduction of Ge halide salts (GeX4) by hydride reducing agents within inverse micelles. Regulation of NC size is achieved by variation of germanium precursor and the strength of hydride reducing agents used. UV-Visible absorbance and photoluminescence spectroscopy showed strong significant quantum confinement effects, with moderate absorption in the UV spectral range, and strong emission in the violet with a marked dependence on excitation wavelength.
21 citations
TL;DR: In this paper, solid-phase crystallization of a densified amorphous Ge layer formed on GeO2-coated insulating substrates was investigated and the resulting polycrystalline Ge layer with a glass substrate consists of large grains (~10 μm) and exhibits a hole mobility as high as 620 cm2 V−1 s−1, despite a low process temperature (500 °C).
Abstract: The highest recorded hole mobility in semiconductor films on insulators has been updated significantly. We investigate the solid-phase crystallization of a densified amorphous Ge layer formed on GeO2-coated insulating substrates. The resulting polycrystalline Ge layer with a glass substrate consists of large grains (~10 μm) and exhibits a hole mobility as high as 620 cm2 V−1 s−1, despite a low process temperature (500 °C). Even for the Ge layer formed on a flexible polyimide substrate at 375 °C, the hole mobility reaches 500 cm2 V−1 s−1. These achievements will aid in realizing advanced electronics, simultaneously allowing for high performance, inexpensiveness, and flexibility.
20 citations
TL;DR: In this paper, the authors investigated the thermal oxidation kinetics of Ge and showed that the results were completely different from that expected from the Deal-Grove model and that Ge is oxidized by GeO2 on Ge instead of O2 at the interface.
Abstract: Thermal oxidation kinetics of Ge was investigated by the 18O tracing study and re-oxidation experiments of the SiO2/GeO2 stacked oxide-layer. The results suggest that Ge oxidation kinetics is completely different from that expected from the Deal-Grove model and that Ge is oxidized by GeO2 on Ge instead of O2 at the interface. This oxidation process forms large amounts of oxygen vacancies in GeO2, which facilitate the diffusion of oxygen atoms in GeO2. This means that oxygen atoms diffuse through GeO2 with an exchange type of process. Based on experimental results, a possible kinetics for Ge oxidation is discussed.
20 citations
TL;DR: In this article, the authors analyzed Ge nanowire (NW) CMOS devices and circuits in detail, including device geometry parameters such as the channel lengths ( $L_{\mathrm{ ch}}$ ) from 100 to 40 nm, a NW height ( $H_{\Mathrm{ NW}$ ) of 10 nm, the NW widths ( $W{\mathm{ NW}}$ ), and the dielectric equivalent oxide thicknesses (EOTs) of 2 and 5 nm, and four types of device operation modes of accumulation mode (
Abstract: In this paper, Ge nanowire (NW) CMOS devices and circuits are analyzed in detail. Various experiment splits are studied, including device geometry parameters such as the channel lengths ( $L_{\mathrm{ ch}}$ ) from 100 to 40 nm, a NW height ( $H_{\mathrm{ NW}}$ ) of 10 nm, the NW widths ( $W_{\mathrm{ NW}}$ ) from 40 to 10 nm, and the dielectric equivalent oxide thicknesses (EOTs) of 2 and 5 nm, and four types of device operation modes of accumulation mode (AM) and inversion mode (IM) n-type MOSFETs and p-type MOSFETs. Benefited from the NW structure with scaled EOT, subthreshold swing (SS) as low as 64 mV/dec and maximum transconductance ( $g_{\max }$ ) as high as $1057~\mu \text{S}/\mu \text{m}$ are obtained on the Ge NW nMOSFETs. The NW pMOSFETs are also realized on the same common substrate. Furthermore, hybrid Ge NW CMOS with AM nMOSFET and IM pMOSFET is demonstrated for the first time on a Si substrate. The highest maximum voltage gain reaches 54 V/V in the Ge NW CMOS inverters.
19 citations
Cites background from "Academic and industry research prog..."
...As one of the most promising candidates for post-Si CMOS, Ge [1]–[3] is quite unique in its high and balanced mobilities for both electrons and holes, and much higher density of states than most of the III–V compounds at conduction band....
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...Promising progresses in Ge MOSFETs research have been realized regarding interfaces [2], [4]–[8], contacts [4], [6], [9], [10], scaling [3], [7], [8], [11], [12], and 3-D channel structures [10]–[13]....
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TL;DR: Germanium (Ge) is a widely distributed but rare element on earth as discussed by the authors, and it is the most widely used form of germanium in the world, compared to other common metals.
Abstract: Germanium (Ge) is a widely distributed but rare element on earth. Organic germanium is the most widely used form of germanium. Compared to the common metal (mercury, cadmium, lead, etc.), o...
19 citations
Cites background from "Academic and industry research prog..."
...…compounds have been extensively used in semiconductor materials, high quality gate media, nanowires, metal oxide, quantum field effect transistor as well as long and short channel transmission (Pei & Cai, 2012; Pillarisetty, 2011; Yamanoi et al., 2012; Yashiki, Miyajima, Yamada, & Konagai, 2006)....
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...Organic germanium and its compounds have been extensively used in semiconductor materials, high quality gate media, nanowires, metal oxide, quantum field effect transistor as well as long and short channel transmission (Pei & Cai, 2012; Pillarisetty, 2011; Yamanoi et al., 2012; Yashiki, Miyajima, Yamada, & Konagai, 2006)....
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References
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01 Dec 2007
TL;DR: In this paper, a 45 nm logic technology is described that for the first time incorporates high-k + metal gate transistors in a high volume manufacturing process, resulting in the highest drive currents yet reported for NMOS and PMOS.
Abstract: A 45 nm logic technology is described that for the first time incorporates high-k + metal gate transistors in a high volume manufacturing process. The transistors feature 1.0 nm EOT high-k gate dielectric, dual band edge workfunction metal gates and third generation strained silicon, resulting in the highest drive currents yet reported for NMOS and PMOS. The technology also features trench contact based local routing, 9 layers of copper interconnect with low-k ILD, low cost 193 nm dry patterning, and 100% Pb-free packaging. Process yield, performance and reliability are demonstrated on 153 Mb SRAM arrays with SRAM cell size of 0.346 mum2, and on multiple microprocessors.
973 citations
08 Dec 2003
TL;DR: In this article, the authors describe a novel strained transistor architecture which is incorporated into a 90nm logic technology on 300mm wafers, which features an epitaxially grown strained SiGe film embedded in the source drain regions.
Abstract: This paper describes the details of a novel strained transistor architecture which is incorporated into a 90nm logic technology on 300mm wafers The unique strained PMOS transistor structure features an epitaxially grown strained SiGe film embedded in the source drain regions Dramatic performance enhancement relative to unstrained devices are reported These transistors have gate length of 45nm and 50nm for NMOS and PMOS respectively, 12nm physical gate oxide and Ni salicide World record PMOS drive currents of 700/spl mu/A//spl mu/m (high V/sub T/) and 800/spl mu/A//spl mu/m (low V/sub T/) at 12V are demonstrated NMOS devices exercise a highly tensile silicon nitride capping layer to induce tensile strain in the NMOS channel region High NMOS drive currents of 126mA//spl mu/m (high VT) and 145mA//spl mu/m (low VT) at 12V are reported The technology is mature and is being ramped into high volume manufacturing to fabricate next generation Pentium/spl reg/ and Intel/spl reg/ Centrino/spl trade/ processor families
729 citations
TL;DR: In this paper, a method of controlling threading dislocation densities in Ge on Si involving graded SiGe layers and chemical-mechanical polishing (CMP) is presented.
Abstract: A method of controlling threading dislocation densities in Ge on Si involving graded SiGe layers and chemical-mechanical polishing (CMP) is presented. This method has allowed us to grow a relaxed graded buffer to 100% Ge without the increase in threading dislocation density normally observed in thick graded structures. This sample has been characterized by transmission electron microscopy, etch-pit density, atomic force microscopy, Nomarski optical microscopy, and triple-axis x-ray diffraction. Compared to other relaxed graded buffers in which CMP was not implemented, this sample exhibits improvements in threading dislocation density and surface roughness. We have also made process modifications in order to eliminate particles due to gas-phase nucleation and cracks due to thermal mismatch strain. We have achieved relaxed Ge on Si with a threading dislocation density of 2.1×106 cm−2, and we expect that further process refinements will lead to lower threading dislocation densities on the order of bulk Ge su...
620 citations
TL;DR: In this article, the opportunities and challenges of high-k/Ge MOSFETs are discussed on the basis of the material properties of Ge oxide to provide insights for future progress.
443 citations