Academic and industry research progress in germanium nanodevices
TL;DR: Germanium-based transistors have the potential to operate at high speeds with low power requirements and might therefore be used in non-silicon-based semiconductor technology in the future.
Abstract: Silicon has enabled the rise of the semiconductor electronics industry, but it was not the first material used in such devices. During the 1950s, just after the birth of the transistor, solid-state devices were almost exclusively manufactured from germanium. Today, one of the key ways to improve transistor performance is to increase charge-carrier mobility within the device channel. Motivated by this, the solid-state device research community is returning to investigating the high-mobility material germanium. Germanium-based transistors have the potential to operate at high speeds with low power requirements and might therefore be used in non-silicon-based semiconductor technology in the future.
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TL;DR: In this paper, the authors demonstrate that phosphorous atomic layer doping in ultra-high vacuum is a viable method to obtain n-type doping of strained germanium-on-insulator thin films.
Abstract: We demonstrate that phosphorous atomic layer doping in ultra-high vacuum is a viable method to obtain n-type doping of strained germanium-on-insulator thin films. By engineering single and multiple, closely-spaced P δ-layers, we obtain high active electron concentrations (∼1 × 1020 cm−3) and low electrical resistivity (∼120 Ω/square) whilst keeping control over doping profile, structural integrity, and tensile strain levels (e = 0.35%). Investigation of magnetotransport over a large temperature range (1.7-290 K) allows observation of two-dimensional electrons' weak localization up to 30 K.
19 citations
TL;DR: In this paper, the effects of the back gate voltage, temperature, device dimensions, and channel doping concentration on the leakage currents of the fabricated devices were experimentally analyzed in detail, which indicated that the leakage current is mainly affected by the gate tunneling current, the Shockley-Read-Hall generation current, and the trap-assisted tunneling currents.
Abstract: Junctionless nanowire transistors (JNTs) have been fabricated on ultra-thin-body germanium-on-insulator (GOI) substrates using a simple Si-compatible top-down process. These JNTs, which have gate lengths and widths that are both less than 100 nm, exhibit good electrical characteristics (Ion/Ioff ratio of ∼105 at Vd = −1 V). The effects of the back gate voltage, temperature, the device dimensions, and the channel doping concentration on the leakage currents of the fabricated devices were experimentally analyzed in detail. The results indicate that the leakage current is mainly affected by the gate tunneling current, the Shockley-Read-Hall generation current, the band-to-band tunneling current and the trap-assisted tunneling current. Design guidelines were then proposed to reduce the leakage currents of GOI-based JNTs.
19 citations
TL;DR: In this article, a radio-frequency ring-shaped hollow cathode discharge has been developed as a candidate for processing plasma sources, which reaches a high magnitude of 1010-1011 cm−3.
Abstract: In order to achieve high-density capacitively coupled plasma, a radio-frequency (RF) ring-shaped hollow cathode discharge has been developed as a candidate for processing plasma sources. The plasma density in the hollow cathode discharge reaches a high magnitude of 1010–1011 cm−3. The RF ring-shaped hollow cathode discharge depends on the pressure and mass of the working gas. Criteria required for producing a RF ring-shaped hollow cathode discharge have been investigated for various gas pressures using H2 and Ar gases for high-density plasma production. The results reveal that the criteria for the occurrence of the hollow cathode effect are that the trench width should be approximately equal to the sum of the electron-neutral mean free paths and twice the sheath thickness of the RF powered electrode.
19 citations
TL;DR: The luminescence quenching mechanism was confirmed by static and time-resolved photoluminescence spectroscopies, while the applicability for this assay for detection of Fe3+ in real water samples was successfully demonstrated.
Abstract: Luminescent water-soluble germanium nanocrystals (Ge NCs) have been developed as a fluorescent sensing platform for the highly selective and sensitive detection of Fe3+via quenching of their strong blue luminescence, without the need for analyte-specific labelling groups. The amine-terminated Ge NCs were separated into two discrete size fractions with average diameters of 3.9 ± 0.4 nm and 6.8 ± 1.8 nm using centrifugation. The smaller 3.9 nm NCs possessed a strong blue luminescence, with an average lifetime of 6.1 ns and a quantum yield (QY) of 21.5%, which is strongly influenced by solution pH. In contrast, 6.8 nm NCs exhibited a green luminescence with a longer lifetime of 7.8 ns and lower QY (6.2%) that is insensitive to pH. Sensitive detection of Fe3+ was successfully demonstrated, with a linear relationship between luminescence quenching and Fe3+ concentration observed from 0–800 μM, with a limit of detection of 0.83 μM. The Ge NCs show excellent selectivity toward Fe3+ ions, with no quenching of the fluorescence signal induced by the presence of Fe2+ ions, allowing for solution phase discrimination between ions of the same element with different formal charges. The luminescence quenching mechanism was confirmed by static and time-resolved photoluminescence spectroscopies, while the applicability for this assay for detection of Fe3+ in real water samples was successfully demonstrated.
19 citations
TL;DR: In this paper, structural and electrical characteristics of epitaxial germanium (Ge) heterogeneously integrated on silicon (Si) via a composite, large bandgap AlAs/GaAs buffer are investigated.
Abstract: Structural and electrical characteristics of epitaxial germanium (Ge) heterogeneously integrated on silicon (Si) via a composite, large bandgap AlAs/GaAs buffer are investigated. Electrical characteristics of N-type metal-oxide-semiconductor (MOS) capacitors, fabricated from the aforementioned material stack are then presented. Simulated and experimental X-ray rocking curves show distinct Ge, AlAs, and GaAs epilayer peaks. Moreover, secondary ion mass spectrometry, energy dispersive X-ray spectroscopy (EDS) profile, and EDS line profile suggest limited interdiffusion of the underlying buffer into the Ge layer, which is further indicative of the successful growth of device-quality epitaxial Ge layer. The Ge MOS capacitor devices demonstrated low frequency dispersion of 1.80% per decade, low frequency-dependent flat-band voltage, $V_{FB}$ , shift of 153 mV, efficient Fermi level movement, and limited C-V stretch out. Low interface state density $(D_{it} )$ from $8.55 \times 10^{11} $ to $1.09 \times 10^{12}~ {\rm cm}^{-2} ~{\rm eV}^{-1} $ is indicative of a high-quality oxide/Ge heterointerface, an effective electrical passivation of the Ge surface, and a Ge epitaxy with minimal defects. These superior electrical and material characteristics suggest the feasibility of utilizing large bandgap III-V buffers in the heterointegration of high-mobility channel materials on Si for future high-speed complementary metal-oxide semiconductor logic applications.
19 citations
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References
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01 Dec 2007
TL;DR: In this paper, a 45 nm logic technology is described that for the first time incorporates high-k + metal gate transistors in a high volume manufacturing process, resulting in the highest drive currents yet reported for NMOS and PMOS.
Abstract: A 45 nm logic technology is described that for the first time incorporates high-k + metal gate transistors in a high volume manufacturing process. The transistors feature 1.0 nm EOT high-k gate dielectric, dual band edge workfunction metal gates and third generation strained silicon, resulting in the highest drive currents yet reported for NMOS and PMOS. The technology also features trench contact based local routing, 9 layers of copper interconnect with low-k ILD, low cost 193 nm dry patterning, and 100% Pb-free packaging. Process yield, performance and reliability are demonstrated on 153 Mb SRAM arrays with SRAM cell size of 0.346 mum2, and on multiple microprocessors.
973 citations
08 Dec 2003
TL;DR: In this article, the authors describe a novel strained transistor architecture which is incorporated into a 90nm logic technology on 300mm wafers, which features an epitaxially grown strained SiGe film embedded in the source drain regions.
Abstract: This paper describes the details of a novel strained transistor architecture which is incorporated into a 90nm logic technology on 300mm wafers The unique strained PMOS transistor structure features an epitaxially grown strained SiGe film embedded in the source drain regions Dramatic performance enhancement relative to unstrained devices are reported These transistors have gate length of 45nm and 50nm for NMOS and PMOS respectively, 12nm physical gate oxide and Ni salicide World record PMOS drive currents of 700/spl mu/A//spl mu/m (high V/sub T/) and 800/spl mu/A//spl mu/m (low V/sub T/) at 12V are demonstrated NMOS devices exercise a highly tensile silicon nitride capping layer to induce tensile strain in the NMOS channel region High NMOS drive currents of 126mA//spl mu/m (high VT) and 145mA//spl mu/m (low VT) at 12V are reported The technology is mature and is being ramped into high volume manufacturing to fabricate next generation Pentium/spl reg/ and Intel/spl reg/ Centrino/spl trade/ processor families
729 citations
TL;DR: In this paper, a method of controlling threading dislocation densities in Ge on Si involving graded SiGe layers and chemical-mechanical polishing (CMP) is presented.
Abstract: A method of controlling threading dislocation densities in Ge on Si involving graded SiGe layers and chemical-mechanical polishing (CMP) is presented. This method has allowed us to grow a relaxed graded buffer to 100% Ge without the increase in threading dislocation density normally observed in thick graded structures. This sample has been characterized by transmission electron microscopy, etch-pit density, atomic force microscopy, Nomarski optical microscopy, and triple-axis x-ray diffraction. Compared to other relaxed graded buffers in which CMP was not implemented, this sample exhibits improvements in threading dislocation density and surface roughness. We have also made process modifications in order to eliminate particles due to gas-phase nucleation and cracks due to thermal mismatch strain. We have achieved relaxed Ge on Si with a threading dislocation density of 2.1×106 cm−2, and we expect that further process refinements will lead to lower threading dislocation densities on the order of bulk Ge su...
620 citations
TL;DR: In this article, the opportunities and challenges of high-k/Ge MOSFETs are discussed on the basis of the material properties of Ge oxide to provide insights for future progress.
443 citations