Academic and industry research progress in germanium nanodevices
TL;DR: Germanium-based transistors have the potential to operate at high speeds with low power requirements and might therefore be used in non-silicon-based semiconductor technology in the future.
Abstract: Silicon has enabled the rise of the semiconductor electronics industry, but it was not the first material used in such devices. During the 1950s, just after the birth of the transistor, solid-state devices were almost exclusively manufactured from germanium. Today, one of the key ways to improve transistor performance is to increase charge-carrier mobility within the device channel. Motivated by this, the solid-state device research community is returning to investigating the high-mobility material germanium. Germanium-based transistors have the potential to operate at high speeds with low power requirements and might therefore be used in non-silicon-based semiconductor technology in the future.
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TL;DR: In this paper, the electron band structures of Ge1−xSnx alloys were calculated using the nonlocal empirical pseudopotential method, and the electron and hole effective masses were extracted.
Abstract: The electron band structures of Ge1−xSnx alloys were calculated using the nonlocal empirical pseudopotential method. The electron and hole effective masses were extracted, and the mobility enhancement over Ge was comprehensively analyzed. For the direct gap Ge1−xSnx with high Sn compositions, only a small fraction of electrons occupy the Γ valley with high mobility at room temperature. Hence, the negative differential mobility resulting from the transferred-electron effect may not be observed, and the electron mobility enhancement over Ge is only two-fold. Low temperature conditions may lead to the transferred-electron effect and a significantly enhanced electron mobility.
16 citations
TL;DR: In this paper, the first experimental demonstration of p-type enhancement-mode FETs fabricated from undoped and catalyst-free Ge nanowires was presented, and the gate-modulated hole concentration was calculated to be on the order of 1018 cm−3.
Abstract: Nominally undoped Ge nanowires were synthesized by a two-step growth method in a low-pressure chemical vapour deposition reactor using a gold nanoparticle-mediated vapour–liquid–solid growth mechanism. The as-grown nanowires were treated by dipping them in an HCl-containing aqueous triiodide solution to remove the gold from the tips and sidewalls of the nanowires. Top-gated field-effect transistors (FETs) fabricated from catalyst-free Ge nanowires (diameters of 20–70 nm and channel lengths of 300–1110 nm) exhibited p-type characteristics as a result of hole accumulation. The gate-modulated hole concentration was calculated to be on the order of 1018 cm−3. On-currents, on/off ratios, transconductances, and field-effect hole mobilities up to 0.29 mA μm−1, 520, 0.44 mS μm−1, and 478 cm2 V−1, respectively, as well as subthreshold slopes of 385 to 580 mV per decade were extracted from these Ge nanowire FETs. These Ge nanowire FETs are expected to exhibit faster intrinsic device speed or gate delay than planar Si p-MOSFETs as the gate length is scaled down to nanometer dimensions. This work provides the first experimental demonstration of p-type enhancement-mode FETs fabricated from undoped and catalyst-free Ge nanowires.
16 citations
06 Jun 2013
TL;DR: In this paper, the authors review the high-concentration doping of Ge materials, including their ability to model such materials, as well as looking at potential future solutions, and discuss the current state of the art in this area.
Abstract: Ideal source and drain regions rely on high dopant solubility in the crystalline substrate, in order to boost activation and reduce sheet resistance, and low dopant diffusivity, to facilitate device scaling. High-concentration doping of Ge can be quite a substantial problem, as it is difficult to activate impurity atoms to a high enough level, prevent them escaping during thermal treatments, while maintaining good crystalline integrity of the semiconductor substrate. With future FET devices fabricated with nanowire, fin, or ultra-thin-body architectures, as reiterated by The International Technology Roadmap for Semiconductors, this problem may be challenging for many years to come. In this paper Ge doping challenges will be reviewed, including our ability to model such materials, as well as looking at potential future solutions.
16 citations
TL;DR: It is found that at a separation of 9 nm the stacked-2DEGs, while interacting, still maintain their individuality in terms of electron transport and show long phase coherence lengths, resulting in an interlayer scattering time much longer than the scattering time within the dopant plane.
Abstract: Stacking of two-dimensional electron gases (2DEGs) obtained by δ-doping of Ge and patterned by scanning probe lithography is a promising approach to realize ultrascaled 3D epitaxial circuits, where multiple layers of active electronic components are integrated both vertically and horizontally. We use atom probe tomography and magnetotransport to correlate the real space 3D atomic distribution of dopants in the crystal with the quantum correction to the conductivity observed at low temperatures, probing if closely stacked δ-layers in Ge behave as independent 2DEGs. We find that at a separation of 9 nm the stacked-2DEGs, while interacting, still maintain their individuality in terms of electron transport and show long phase coherence lengths (∼220 nm). Strong vertical electron confinement is crucial to this finding, resulting in an interlayer scattering time much longer (∼1000 × ) than the scattering time within the dopant plane.
16 citations
TL;DR: All electronic transitions giving rise to experimental anion photoelectron bands in the spectrum of TiGe2- can now be assigned and the X band of the anionphotoelectron spectrum is attributed to a one-electron transition between two ground states 4B1 → 3B1.
Abstract: Electronic structures of both the anionic and neutral triatomic species TiGe2-/0 were theoretically studied employing single-reference (DFT and RCCSD(T)) and multiconfigurational (CASSCF/CASPT2 and CASSCF/NEVPT2) methods with large basis sets. The ground state of TiGe2- (C2v) was identified to be 4B1, but the 2A1 state is nearly degenerate, whereas the 3B1 is clearly the ground state of the neutral TiGe2 (C2v). On the basis of the computed ground and excited states of both neutral and anionic structures, all electronic transitions giving rise to experimental anion photoelectron bands in the spectrum of TiGe2- can now be assigned. The X band of the anion photoelectron spectrum is attributed to a one-electron transition between two ground states 4B1 → 3B1. Three neutral excited states 23A2, 25B1, and 35B1 are energetically responsible for the B band upon one-electron photodetachement from the anionic ground state 4B1. The C band is assigned to the transition 4B1 → 25A1. A transition from the nearly degenerate ground state 2A1 of the anion to the low-spin 1A1 of the final neutral state can be ascribed to the A band. Furthermore, the first two bands' progressions, whose normal vibrational modes were accessible from CASSCF/CASPT2 calculations, were also simulated by determination of multidimensional Franck-Condon factors.
16 citations
References
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01 Dec 2007
TL;DR: In this paper, a 45 nm logic technology is described that for the first time incorporates high-k + metal gate transistors in a high volume manufacturing process, resulting in the highest drive currents yet reported for NMOS and PMOS.
Abstract: A 45 nm logic technology is described that for the first time incorporates high-k + metal gate transistors in a high volume manufacturing process. The transistors feature 1.0 nm EOT high-k gate dielectric, dual band edge workfunction metal gates and third generation strained silicon, resulting in the highest drive currents yet reported for NMOS and PMOS. The technology also features trench contact based local routing, 9 layers of copper interconnect with low-k ILD, low cost 193 nm dry patterning, and 100% Pb-free packaging. Process yield, performance and reliability are demonstrated on 153 Mb SRAM arrays with SRAM cell size of 0.346 mum2, and on multiple microprocessors.
973 citations
08 Dec 2003
TL;DR: In this article, the authors describe a novel strained transistor architecture which is incorporated into a 90nm logic technology on 300mm wafers, which features an epitaxially grown strained SiGe film embedded in the source drain regions.
Abstract: This paper describes the details of a novel strained transistor architecture which is incorporated into a 90nm logic technology on 300mm wafers The unique strained PMOS transistor structure features an epitaxially grown strained SiGe film embedded in the source drain regions Dramatic performance enhancement relative to unstrained devices are reported These transistors have gate length of 45nm and 50nm for NMOS and PMOS respectively, 12nm physical gate oxide and Ni salicide World record PMOS drive currents of 700/spl mu/A//spl mu/m (high V/sub T/) and 800/spl mu/A//spl mu/m (low V/sub T/) at 12V are demonstrated NMOS devices exercise a highly tensile silicon nitride capping layer to induce tensile strain in the NMOS channel region High NMOS drive currents of 126mA//spl mu/m (high VT) and 145mA//spl mu/m (low VT) at 12V are reported The technology is mature and is being ramped into high volume manufacturing to fabricate next generation Pentium/spl reg/ and Intel/spl reg/ Centrino/spl trade/ processor families
729 citations
TL;DR: In this paper, a method of controlling threading dislocation densities in Ge on Si involving graded SiGe layers and chemical-mechanical polishing (CMP) is presented.
Abstract: A method of controlling threading dislocation densities in Ge on Si involving graded SiGe layers and chemical-mechanical polishing (CMP) is presented. This method has allowed us to grow a relaxed graded buffer to 100% Ge without the increase in threading dislocation density normally observed in thick graded structures. This sample has been characterized by transmission electron microscopy, etch-pit density, atomic force microscopy, Nomarski optical microscopy, and triple-axis x-ray diffraction. Compared to other relaxed graded buffers in which CMP was not implemented, this sample exhibits improvements in threading dislocation density and surface roughness. We have also made process modifications in order to eliminate particles due to gas-phase nucleation and cracks due to thermal mismatch strain. We have achieved relaxed Ge on Si with a threading dislocation density of 2.1×106 cm−2, and we expect that further process refinements will lead to lower threading dislocation densities on the order of bulk Ge su...
620 citations
TL;DR: In this article, the opportunities and challenges of high-k/Ge MOSFETs are discussed on the basis of the material properties of Ge oxide to provide insights for future progress.
443 citations