Academic and industry research progress in germanium nanodevices
TL;DR: Germanium-based transistors have the potential to operate at high speeds with low power requirements and might therefore be used in non-silicon-based semiconductor technology in the future.
Abstract: Silicon has enabled the rise of the semiconductor electronics industry, but it was not the first material used in such devices. During the 1950s, just after the birth of the transistor, solid-state devices were almost exclusively manufactured from germanium. Today, one of the key ways to improve transistor performance is to increase charge-carrier mobility within the device channel. Motivated by this, the solid-state device research community is returning to investigating the high-mobility material germanium. Germanium-based transistors have the potential to operate at high speeds with low power requirements and might therefore be used in non-silicon-based semiconductor technology in the future.
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TL;DR: In this article, a bottom-up approach is used to demonstrate the 3D assembly of atomically sharp doping profiles in germanium by a repeated stacking of two-dimensional (2D) high-density phosphorus layers.
Abstract: Extending chip performance beyond current limits of miniaturisation requires new materials and functionalities that integrate well with the silicon platform. Germanium fits these requirements and has been proposed as a high-mobility channel material, a light emitting medium in silicon-integrated lasers, and a plasmonic conductor for bio-sensing. Common to these diverse applications is the need for homogeneous, high electron densities in three-dimensions (3D). Here we use a bottom-up approach to demonstrate the 3D assembly of atomically sharp doping profiles in germanium by a repeated stacking of two-dimensional (2D) high-density phosphorus layers. This produces high-density (10(19) to 10(20) cm(-3)) low-resistivity (10(-4)Ω · cm) metallic germanium of precisely defined thickness, beyond the capabilities of diffusion-based doping technologies. We demonstrate that free electrons from distinct 2D dopant layers coalesce into a homogeneous 3D conductor using anisotropic quantum interference measurements, atom probe tomography, and density functional theory.
16 citations
16 citations
TL;DR: In this paper, the temperature dependence of the Shubnikov-de Haas oscillations was used to obtain the effective g factor of low-density two-dimensional holes in a Ge quantum well.
Abstract: We report the measurements of the effective g factor of low-density two-dimensional holes in a Ge quantum well. Using the temperature dependence of the Shubnikov-de Haas oscillations, we extract the effective g factor in a magnetic field perpendicular to the sample surface. Very large values of the effective g factor, ranging from ∼13 to ∼28, are observed in the density range of 1.4×1010 cm−2– 1.4×1011 cm−2. When the magnetic field is oriented parallel to the sample surface, the effective g factor is obtained from a protrusion in the magneto-resistance data that signify full spin polarization. In the latter orientation, a small effective g factor, ∼1.3−1.4, is measured in the density range of 1.5×1010 cm−2– 2×1010 cm−2. This very strong anisotropy is consistent with theoretical predictions and previous measurements in other 2D hole systems, such as InGaAs and GaSb.
15 citations
TL;DR: This study seems to successfully provide the conditions in growing either GaON-dominated or Ga2O3-dominated structure by a simple and low-cost ECD.
Abstract: We report the growth of gallium-based compounds, i.e., gallium oxynitride (GaON) and gallium oxide (Ga2O3) on multilayer graphene (MLG) on insulator using a mixture of ammonium nitrate (NH4NO3) and gallium nitrate (Ga(NO3)3) by electrochemical deposition (ECD) method at room temperature (RT) for the first time. The controlling parameters of current density and electrolyte molarity were found to greatly influence the properties of the grown structures. The thicknesses of the deposited structures increase with the current density since it increases the chemical reaction rates. The layers grown at low molarities of both solutions basically show grain-like layer with cracking structures and dominated by both Ga2O3 and GaON. Such cracking structures seem to diminish with the increases of molarities of one of the solutions. It is speculated that the increase of current density and ions in the solutions helps to promote the growth at the area with uneven thicknesses of graphene. When the molarity of Ga(NO3)3 is increased while keeping the molarity of NH4NO3 at the lowest value of 2.5 M, the grown structures are basically dominated by the Ga2O3 structure. On the other hand, when the molarity of NH4NO3 is increased while keeping the molarity of Ga(NO3)3 at the lowest value of 0.8 M, the GaON structure seems to dominate where their cubic and hexagonal arrangements are coexisting. It was found that when the molarities of Ga(NO3)3 are at the high level of 7.5 M, the grown structures tend to be dominated by Ga2O3 even though the molarity of NH4NO3 is made equal or higher than the molarity of Ga(NO3)3. When the grown structure is dominated by the Ga2O3 structure, the deposition process became slow or unstable, resulting to the formation of thin layer. When the molarity of Ga(NO3)3 is increased to 15 M, the nanocluster-like structures were formed instead of continuous thin film structure. This study seems to successfully provide the conditions in growing either GaON-dominated or Ga2O3-dominated structure by a simple and low-cost ECD. The next possible routes to convert the grown GaON-dominated structure to either single-crystalline GaN or Ga2O3 as well as Ga2O3-dominated structure to single-crystalline Ga2O3 structure have been discussed.
15 citations
Cites methods from "Academic and industry research prog..."
...Background The performance of silicon ultra-large-scale integrated circuits (Si-ULSIs) has been enhanced over the last 30 years by increasing the number of transistors in accordance with Moore’s law [1]....
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01 May 2018
TL;DR: In this paper, a review draws together recent advances in supramolecular gels with an emphasis on their proposed uses as optoelectronic, energy, biomedical, and biological materials.
Abstract: Traditionally, gels have been defined by their covalently cross-linked polymer networks. Supramolecular gels challenge this framework by relying on non-covalent interactions for self-organization into hierarchical structures. This class of materials offers a variety of novel and exciting potential applications. This review draws together recent advances in supramolecular gels with an emphasis on their proposed uses as optoelectronic, energy, biomedical, and biological materials. Additional special topics reviewed include environmental remediation, participation in synthesis procedures, and other industrial uses. The examples presented here demonstrate unique benefits of supramolecular gels, including tunability, processability, and self-healing capability, enabling a new approach to solve engineering challenges.
15 citations
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01 Dec 2007
TL;DR: In this paper, a 45 nm logic technology is described that for the first time incorporates high-k + metal gate transistors in a high volume manufacturing process, resulting in the highest drive currents yet reported for NMOS and PMOS.
Abstract: A 45 nm logic technology is described that for the first time incorporates high-k + metal gate transistors in a high volume manufacturing process. The transistors feature 1.0 nm EOT high-k gate dielectric, dual band edge workfunction metal gates and third generation strained silicon, resulting in the highest drive currents yet reported for NMOS and PMOS. The technology also features trench contact based local routing, 9 layers of copper interconnect with low-k ILD, low cost 193 nm dry patterning, and 100% Pb-free packaging. Process yield, performance and reliability are demonstrated on 153 Mb SRAM arrays with SRAM cell size of 0.346 mum2, and on multiple microprocessors.
973 citations
08 Dec 2003
TL;DR: In this article, the authors describe a novel strained transistor architecture which is incorporated into a 90nm logic technology on 300mm wafers, which features an epitaxially grown strained SiGe film embedded in the source drain regions.
Abstract: This paper describes the details of a novel strained transistor architecture which is incorporated into a 90nm logic technology on 300mm wafers The unique strained PMOS transistor structure features an epitaxially grown strained SiGe film embedded in the source drain regions Dramatic performance enhancement relative to unstrained devices are reported These transistors have gate length of 45nm and 50nm for NMOS and PMOS respectively, 12nm physical gate oxide and Ni salicide World record PMOS drive currents of 700/spl mu/A//spl mu/m (high V/sub T/) and 800/spl mu/A//spl mu/m (low V/sub T/) at 12V are demonstrated NMOS devices exercise a highly tensile silicon nitride capping layer to induce tensile strain in the NMOS channel region High NMOS drive currents of 126mA//spl mu/m (high VT) and 145mA//spl mu/m (low VT) at 12V are reported The technology is mature and is being ramped into high volume manufacturing to fabricate next generation Pentium/spl reg/ and Intel/spl reg/ Centrino/spl trade/ processor families
729 citations
TL;DR: In this paper, a method of controlling threading dislocation densities in Ge on Si involving graded SiGe layers and chemical-mechanical polishing (CMP) is presented.
Abstract: A method of controlling threading dislocation densities in Ge on Si involving graded SiGe layers and chemical-mechanical polishing (CMP) is presented. This method has allowed us to grow a relaxed graded buffer to 100% Ge without the increase in threading dislocation density normally observed in thick graded structures. This sample has been characterized by transmission electron microscopy, etch-pit density, atomic force microscopy, Nomarski optical microscopy, and triple-axis x-ray diffraction. Compared to other relaxed graded buffers in which CMP was not implemented, this sample exhibits improvements in threading dislocation density and surface roughness. We have also made process modifications in order to eliminate particles due to gas-phase nucleation and cracks due to thermal mismatch strain. We have achieved relaxed Ge on Si with a threading dislocation density of 2.1×106 cm−2, and we expect that further process refinements will lead to lower threading dislocation densities on the order of bulk Ge su...
620 citations
TL;DR: In this article, the opportunities and challenges of high-k/Ge MOSFETs are discussed on the basis of the material properties of Ge oxide to provide insights for future progress.
443 citations