Academic and industry research progress in germanium nanodevices
TL;DR: Germanium-based transistors have the potential to operate at high speeds with low power requirements and might therefore be used in non-silicon-based semiconductor technology in the future.
Abstract: Silicon has enabled the rise of the semiconductor electronics industry, but it was not the first material used in such devices. During the 1950s, just after the birth of the transistor, solid-state devices were almost exclusively manufactured from germanium. Today, one of the key ways to improve transistor performance is to increase charge-carrier mobility within the device channel. Motivated by this, the solid-state device research community is returning to investigating the high-mobility material germanium. Germanium-based transistors have the potential to operate at high speeds with low power requirements and might therefore be used in non-silicon-based semiconductor technology in the future.
Citations
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TL;DR: In this paper, the spin Seebeck effect in a germanene p-n junction was studied by using the nonequilibrium Green's function method combined with the tight-binding Hamiltonian.
Abstract: Spin Seebeck effect in a germanene p-n junction is studied by using the nonequilibrium Green's function method combined with the tight-binding Hamiltonian. We find that the thermal bias ΔT can generate spin thermopower when a local exchange field is applied on one edge of the germanene nano-ribbon. The magnitude of the spin thermopower can be modulated by the potential drop across the two terminals of the p-n junction. When the value of the potential drop is smaller than the spin-orbit interaction strength, the spin thermopower is enhanced by two orders of magnitude larger as compared to the case of zero p-n voltage. Optimal temperature corresponding to maximum spin thermopower is insensitive to the potential drop. In the p-n region, maximum spin thermopower can be obtained at relatively higher temperatures. When the value of the potential drop is larger than that of the spin-orbit interaction, however, the spin Seebeck effect decays rapidly with increasing potential drop or temperature. By optimizing the structure parameters, the magnitude of the spin thermopower can be remarkably enhanced due to the coexistence of the exchange field and the potential drop.
13 citations
TL;DR: In this article, the configuration, stability, evolution, and electronic properties of neutral and cationic [AuGen]λ and [Gen+1]λ (n=1−13, λ=0, +1) nanoalloy clusters have been systematically investigated by using unbiased global search technique married with double-density functional strategy.
Abstract: The configuration, stability, evolution, and electronic properties of neutral and cationic [AuGen]λ and [Gen+1]λ (n=1−13, λ=0, +1) nanoalloy clusters have been systematically investigated by using unbiased global search technique married with double-density functional strategy. The results reveal that although the neutral and cationic global minimal structures of gold-doped germanium clusters differ from each other when n=4, and 6–13, the evolution patterns are consistent. Attaching structures have been changed to Au-encapsulated motif at the turning point of n=11. The analyses of electronic structure and binding energy indicate that doping of an Au atom may decrease the stability of neutral Ge nanoclusters, but can enhance the stability of cationic Ge nanoclusters. The analyses of electronic property show that ionization potentials (IP) of Gen+1 cluster are larger than those of AuGen nanoalloy clusters, indicating that doping of an Au atom can decrease the ionization potential of neutral Ge nanoclusters. The analyses of HOMO and LUMO energy reveal that HOMO-LUMO gaps of neutral AuGen (n=1−13) with the exception of n=2 and 3 are smaller than that of Gen+1 clusters. For cations, the HOMO-LUMO gaps of [AuGen]+ are wider than that of [Gen+1]+ cluster when n=2, 5–7, and 9–11, narrower when n=3, 4, 8 and 13, and nearly identical when n=1 and 12. The PBE-DFT based global descriptors viz. Electronegativity, Hardness, Softness and Electrophilicity Index of [Gen+1]λ and [AuGen]λ (λ=0, +1; n=1−13) nanoclusters are estimated by means of HOMO-LUMO gap. And they possess highly correlation with HOMO-LUMO gap. The agreement between theoretical and experimental results such as IP, binding energy, HOMO-LUMO gap, and bond distance demonstrate the success of the computational analyses in this work.
13 citations
TL;DR: In this paper, the influence of hollow-cathode trench shape on high-density plasma production has been investigated at a wide range of argon gas pressure and various input powers.
Abstract: High-density radio-frequency (RF) plasma sources have been produced by ring-shaped hollow-cathode discharge at various trench shapes. The influence of hollow-cathode trench shape on high-density plasma production has been investigated at a wide range of argon gas pressure and various input powers. The trench shapes are selected from well-typed, taper-typed, step-typed, and three improved step-typed trench shapes. It is revealed that, at the lower pressure less than 200 mtorr, the plasma density for the well-typed shape is the highest among the three shapes, while for the step-typed shape, it is the lowest. For the higher pressure more than 200 mtorr, the plasma density for the step-typed shape has the highest value. The results indicate that the plasma density for all typed shapes is almost proportional to RF input power. It is found that the improved step-typed trench shapes can attain a wide range of gas pressure sustaining higher plasma density.
13 citations
Additional excerpts
...CAPACITIVELY COUPLED plasma sources [1]–[3] have been widely used compared with other plasma sources [4], [5] for plasma dry etching [6], plasma-enhanced chemical vapor deposition [6], and physical and reactive sputtering [7] processes nowadays....
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TL;DR: Ge/Si CSNWs can have the type-I band alignment characteristics by the band structure engineering, which enables both n-type and p-type quantum-well transistors to be fabricated using Ge/SiCSNWs for high-speed logic applications.
Abstract: We investigate the electronic band structures of Ge/Si core-shell nanowires (CSNWs) and devise a way to realize the electron quantum well at Ge core atoms with first-principles calculations. We reveal that the electronic band engineering by the quantum confinement and the lattice strain can induce the type-I/II band alignment transition, and the resulting type-I band alignment generates the electron quantum well in Ge/Si CSNWs. We also find that the type-I/II transition in Ge/Si CSNWs is highly related to the direct to indirect band gap transition through the analysis of charge density and band structures. In terms of the quantum confinement, for [100] and [111] directional Ge/Si CSNWs, the type-I/II transition can be obtained by decreasing the diameters, whereas a [110] directional CSNW preserves the type-II band alignment even at diameters as small as 1 nm. By applying a compressive strain on [110] CSNWs, the type-I band alignment can be formed. Our results suggest that Ge/Si CSNWs can have the type-I band alignment characteristics by the band structure engineering, which enables both n-type and p-type quantum-well transistors to be fabricated using Ge/Si CSNWs for high-speed logic applications.
13 citations
TL;DR: A detailed, informative and comprehensive review of germanium recovery has been carried out in this paper , where the dissolution properties of various phases of Germanium are presented in detail.
13 citations
References
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01 Dec 2007
TL;DR: In this paper, a 45 nm logic technology is described that for the first time incorporates high-k + metal gate transistors in a high volume manufacturing process, resulting in the highest drive currents yet reported for NMOS and PMOS.
Abstract: A 45 nm logic technology is described that for the first time incorporates high-k + metal gate transistors in a high volume manufacturing process. The transistors feature 1.0 nm EOT high-k gate dielectric, dual band edge workfunction metal gates and third generation strained silicon, resulting in the highest drive currents yet reported for NMOS and PMOS. The technology also features trench contact based local routing, 9 layers of copper interconnect with low-k ILD, low cost 193 nm dry patterning, and 100% Pb-free packaging. Process yield, performance and reliability are demonstrated on 153 Mb SRAM arrays with SRAM cell size of 0.346 mum2, and on multiple microprocessors.
973 citations
08 Dec 2003
TL;DR: In this article, the authors describe a novel strained transistor architecture which is incorporated into a 90nm logic technology on 300mm wafers, which features an epitaxially grown strained SiGe film embedded in the source drain regions.
Abstract: This paper describes the details of a novel strained transistor architecture which is incorporated into a 90nm logic technology on 300mm wafers The unique strained PMOS transistor structure features an epitaxially grown strained SiGe film embedded in the source drain regions Dramatic performance enhancement relative to unstrained devices are reported These transistors have gate length of 45nm and 50nm for NMOS and PMOS respectively, 12nm physical gate oxide and Ni salicide World record PMOS drive currents of 700/spl mu/A//spl mu/m (high V/sub T/) and 800/spl mu/A//spl mu/m (low V/sub T/) at 12V are demonstrated NMOS devices exercise a highly tensile silicon nitride capping layer to induce tensile strain in the NMOS channel region High NMOS drive currents of 126mA//spl mu/m (high VT) and 145mA//spl mu/m (low VT) at 12V are reported The technology is mature and is being ramped into high volume manufacturing to fabricate next generation Pentium/spl reg/ and Intel/spl reg/ Centrino/spl trade/ processor families
729 citations
TL;DR: In this paper, a method of controlling threading dislocation densities in Ge on Si involving graded SiGe layers and chemical-mechanical polishing (CMP) is presented.
Abstract: A method of controlling threading dislocation densities in Ge on Si involving graded SiGe layers and chemical-mechanical polishing (CMP) is presented. This method has allowed us to grow a relaxed graded buffer to 100% Ge without the increase in threading dislocation density normally observed in thick graded structures. This sample has been characterized by transmission electron microscopy, etch-pit density, atomic force microscopy, Nomarski optical microscopy, and triple-axis x-ray diffraction. Compared to other relaxed graded buffers in which CMP was not implemented, this sample exhibits improvements in threading dislocation density and surface roughness. We have also made process modifications in order to eliminate particles due to gas-phase nucleation and cracks due to thermal mismatch strain. We have achieved relaxed Ge on Si with a threading dislocation density of 2.1×106 cm−2, and we expect that further process refinements will lead to lower threading dislocation densities on the order of bulk Ge su...
620 citations
TL;DR: In this article, the opportunities and challenges of high-k/Ge MOSFETs are discussed on the basis of the material properties of Ge oxide to provide insights for future progress.
443 citations