Academic and industry research progress in germanium nanodevices
TL;DR: Germanium-based transistors have the potential to operate at high speeds with low power requirements and might therefore be used in non-silicon-based semiconductor technology in the future.
Abstract: Silicon has enabled the rise of the semiconductor electronics industry, but it was not the first material used in such devices. During the 1950s, just after the birth of the transistor, solid-state devices were almost exclusively manufactured from germanium. Today, one of the key ways to improve transistor performance is to increase charge-carrier mobility within the device channel. Motivated by this, the solid-state device research community is returning to investigating the high-mobility material germanium. Germanium-based transistors have the potential to operate at high speeds with low power requirements and might therefore be used in non-silicon-based semiconductor technology in the future.
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TL;DR: The current status of High K dielectrics in Very Large Scale Integrated circuit (VLSI) manufacturing for leading edge Dynamic Random Access Memory (DRAM) and Complementary Metal Oxide Semiconductor (CMOS) applications is summarized along with the deposition methods and general equipment types employed.
Abstract: The current status of High K dielectrics in Very Large Scale Integrated circuit (VLSI) manufacturing for leading edge Dynamic Random Access Memory (DRAM) and Complementary Metal Oxide Semiconductor (CMOS) applications is summarized along with the deposition methods and general equipment types employed. Emerging applications for High K dielectrics in future CMOS are described as well for implementations in 10 nm and beyond nodes. Additional emerging applications for High K dielectrics include Resistive RAM memories, Metal-Insulator-Metal (MIM) diodes, Ferroelectric logic and memory devices, and as mask layers for patterning. Atomic Layer Deposition (ALD) is a common and proven deposition method for all of the applications discussed for use in future VLSI manufacturing.
121 citations
Cites background or methods from "Academic and industry research prog..."
...for the PFET channel [71,72] and III–V materials, particularly InGaAs for the NFET channel of the MOSFET [73,74]....
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...The use of a Si cap over the Ge channel seems to represent a leading approach for passivating interface defects and allows the use of the same High K dielectric stacks used for Si [71,72]....
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TL;DR: An interesting coincidence of a critical thickness of 10 nm was identified in both the CVD growth behavior and in the breakdown electric field strength and leakage current mechanism, indicating that the electrical properties of the cVD h-BN film depended significantly on the film growth mode and the resultant film quality.
Abstract: Two different growth modes of large-area hexagonal boron nitride (h-BN) film, a conventional chemical vapor deposition (CVD) growth mode and a high-pressure CVD growth mode, were compared as a function of the precursor partial pressure. Conventional self-limited CVD growth was obtained below a critical partial pressure of the borazine precursor, whereas a thick h-BN layer (thicker than a critical thickness of 10 nm) was grown beyond a critical partial pressure. An interesting coincidence of a critical thickness of 10 nm was identified in both the CVD growth behavior and in the breakdown electric field strength and leakage current mechanism, indicating that the electrical properties of the CVD h-BN film depended significantly on the film growth mode and the resultant film quality.
116 citations
TL;DR: A germanium-thin-film-based flexible metaphotonic device for ultrafast optical switching of terahertz radiation is experimentally demonstrated, with a resonant transmission modulation depth of 90% and an ultrafast full recovery time of 17 ps.
Abstract: Incorporating semiconductors as active media into metamaterials offers opportunities for a wide range of dynamically switchable/tunable, technologically relevant optical functionalities enabled by strong, resonant light-matter interactions within the semiconductor. Here, a germanium-thin-film-based flexible metaphotonic device for ultrafast optical switching of terahertz radiation is experimentally demonstrated. A resonant transmission modulation depth of 90% is achieved, with an ultrafast full recovery time of 17 ps. An observed sub-picosecond decay constant of 670 fs is attributed to the presence of trap-assisted recombination sites in the thermally evaporated germanium film.
111 citations
TL;DR: In this paper, the authors integrate gate-defined quantum dots and superconductivity into germanium heterostructures and demonstrate electric gate-control of the supercurrent in a quantum well.
Abstract: Superconductors and semiconductors are crucial platforms in the field of quantum computing. They can be combined to hybrids, bringing together physical properties that enable the discovery of new emergent phenomena and provide novel strategies for quantum control. The involved semiconductor materials, however, suffer from disorder, hyperfine interactions or lack of planar technology. Here we realise an approach that overcomes these issues altogether and integrate gate-defined quantum dots and superconductivity into germanium heterostructures. In our system, heavy holes with mobilities exceeding 500,000 cm2 (Vs)−1 are confined in shallow quantum wells that are directly contacted by annealed aluminium leads. We observe proximity-induced superconductivity in the quantum well and demonstrate electric gate-control of the supercurrent. Germanium therefore has great promise for fast and coherent quantum hardware and, being compatible with standard manufacturing, could become a leading material for quantum information processing.
108 citations
TL;DR: In this article, the channel width scaling of back-gated MoS2 metal-oxide-semiconductor field effect transistors (MOSFETs) was studied.
Abstract: We study the channel width scaling of back-gated MoS2 metal-oxide-semiconductor field-effect transistors (MOSFETs) from 2 {\mu}m down to 60 nm. We reveal that the channel conductance scales linearly with channel width, indicating no evident edge damage for MoS2 nanoribbons with widths down to 60 nm as defined by plasma dry etching. However, these transistors show a strong positive threshold voltage (VT) shift with narrow channel widths of less than 200 nm. Our results also show that transistors with thinner channel thicknesses have larger VT shifts associated with width scaling. Devices fabricated on a 6 nm thick MoS2 crystal underwent the transition from depletion-mode to enhancement-mode.
103 citations
Cites background from "Academic and industry research prog..."
...They have been widely studied for logic applications in the past years [1]–[4]....
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References
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01 Dec 2007
TL;DR: In this paper, a 45 nm logic technology is described that for the first time incorporates high-k + metal gate transistors in a high volume manufacturing process, resulting in the highest drive currents yet reported for NMOS and PMOS.
Abstract: A 45 nm logic technology is described that for the first time incorporates high-k + metal gate transistors in a high volume manufacturing process. The transistors feature 1.0 nm EOT high-k gate dielectric, dual band edge workfunction metal gates and third generation strained silicon, resulting in the highest drive currents yet reported for NMOS and PMOS. The technology also features trench contact based local routing, 9 layers of copper interconnect with low-k ILD, low cost 193 nm dry patterning, and 100% Pb-free packaging. Process yield, performance and reliability are demonstrated on 153 Mb SRAM arrays with SRAM cell size of 0.346 mum2, and on multiple microprocessors.
973 citations
08 Dec 2003
TL;DR: In this article, the authors describe a novel strained transistor architecture which is incorporated into a 90nm logic technology on 300mm wafers, which features an epitaxially grown strained SiGe film embedded in the source drain regions.
Abstract: This paper describes the details of a novel strained transistor architecture which is incorporated into a 90nm logic technology on 300mm wafers The unique strained PMOS transistor structure features an epitaxially grown strained SiGe film embedded in the source drain regions Dramatic performance enhancement relative to unstrained devices are reported These transistors have gate length of 45nm and 50nm for NMOS and PMOS respectively, 12nm physical gate oxide and Ni salicide World record PMOS drive currents of 700/spl mu/A//spl mu/m (high V/sub T/) and 800/spl mu/A//spl mu/m (low V/sub T/) at 12V are demonstrated NMOS devices exercise a highly tensile silicon nitride capping layer to induce tensile strain in the NMOS channel region High NMOS drive currents of 126mA//spl mu/m (high VT) and 145mA//spl mu/m (low VT) at 12V are reported The technology is mature and is being ramped into high volume manufacturing to fabricate next generation Pentium/spl reg/ and Intel/spl reg/ Centrino/spl trade/ processor families
729 citations
TL;DR: In this paper, a method of controlling threading dislocation densities in Ge on Si involving graded SiGe layers and chemical-mechanical polishing (CMP) is presented.
Abstract: A method of controlling threading dislocation densities in Ge on Si involving graded SiGe layers and chemical-mechanical polishing (CMP) is presented. This method has allowed us to grow a relaxed graded buffer to 100% Ge without the increase in threading dislocation density normally observed in thick graded structures. This sample has been characterized by transmission electron microscopy, etch-pit density, atomic force microscopy, Nomarski optical microscopy, and triple-axis x-ray diffraction. Compared to other relaxed graded buffers in which CMP was not implemented, this sample exhibits improvements in threading dislocation density and surface roughness. We have also made process modifications in order to eliminate particles due to gas-phase nucleation and cracks due to thermal mismatch strain. We have achieved relaxed Ge on Si with a threading dislocation density of 2.1×106 cm−2, and we expect that further process refinements will lead to lower threading dislocation densities on the order of bulk Ge su...
620 citations
TL;DR: In this article, the opportunities and challenges of high-k/Ge MOSFETs are discussed on the basis of the material properties of Ge oxide to provide insights for future progress.
443 citations