Academic and industry research progress in germanium nanodevices
TL;DR: Germanium-based transistors have the potential to operate at high speeds with low power requirements and might therefore be used in non-silicon-based semiconductor technology in the future.
Abstract: Silicon has enabled the rise of the semiconductor electronics industry, but it was not the first material used in such devices. During the 1950s, just after the birth of the transistor, solid-state devices were almost exclusively manufactured from germanium. Today, one of the key ways to improve transistor performance is to increase charge-carrier mobility within the device channel. Motivated by this, the solid-state device research community is returning to investigating the high-mobility material germanium. Germanium-based transistors have the potential to operate at high speeds with low power requirements and might therefore be used in non-silicon-based semiconductor technology in the future.
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TL;DR: In this paper, the diffusion of oxygen and its interactions with dopants during laser thermal annealing (LTA) in the melting regime is investigated, and it is concluded that O does not interact with As nor in the melt, nor in a solid phase during the cooling transient.
12 citations
TL;DR: In this article, a hot-mesh chemical vapor deposition (HM-CVD) technique was used to grow the silicon carbide-on-insulator (SiCOI) structure using polycrystalline single layer graphene (SLG) as a buffer layer.
Abstract: We report an innovative technique for growing the silicon carbide-on-insulator (SiCOI) structure by utilizing polycrystalline single layer graphene (SLG) as a buffer layer. The epitaxial growth was carried out using a hot-mesh chemical vapor deposition (HM-CVD) technique. Cubic SiC (3C-SiC) thin film in (111) domain was realized at relatively low substrate temperature of 750 °C. 3C-SiC energy bandgap of 2.2 eV was confirmed. The Si-O absorption band observed in the grown film can be caused by the out-diffusion of the oxygen atom from SiO2 substrate or oxygen doping during the cleaning process. Further experimental works by optimizing the cleaning process, growth parameters of the present growth method, or by using other growth methods, as well, are expected to realize a high quality SiCOI structure, thereby opening up the way for a breakthrough in the development of advanced ULSIs with multifunctionalities.
12 citations
Cites background or methods from "Academic and industry research prog..."
...The transistor number in the latest processor of ultra-LSIs (ULSIs) is already over one billion [1]....
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...The performance of silicon large-scale integrated circuits (Si-LSIs) has been enhanced over the last 30 years by increasing the number of transistors in accordance with Moore’s law [1]....
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TL;DR: A self doping contact consisting of a silver/antimony alloy that produces an Ohmic contact to moderately doped n-type germanium (doped to a factor of four above the metal-insulator transition) has been investigated in this paper.
Abstract: A self doping contact consisting of a silver/antimony alloy that produces an Ohmic contact to moderately doped n-type germanium (doped to a factor of four above the metal-insulator transition) has been investigated. An evaporation of a mixed alloy of Ag/Sb (99%/1%) onto n-Ge ( ND=1×1018 cm−3) annealed at 400 °C produces an Ohmic contact with a measured specific contact resistivity of (1.1±0.2)×10−5 Ω-cm2. It is proposed that the Ohmic behaviour arises from an increased doping concentration at the Ge surface due to the preferential evaporation of Sb confirmed by transmission electron microscope analysis. It is suggested that the doping concentration has increased to a level where field emission will be the dominate conduction mechanism. This was deduced from the low temperature electrical characterisation of the contact, which exhibits Ohmic behaviour down to a temperature of 6.5 K.
12 citations
TL;DR: In this article, the impact of AlGaAs and AlAs buffer layers on the electrical properties of an epitaxial gallium-arsenide (epi-GaAs) metal-oxide-semiconductor capacitor (MOSC) was investigated.
Abstract: The impact of AlGaAs and AlAs buffer layers on the electrical properties of an epitaxial gallium-arsenide (epi-GaAs) metal-oxide-semiconductor capacitor (MOSC) was investigated. MOSC was fabricated by using atomic-layer-deposited Al2O3 -TiO2 (TiAlO) alloy gate dielectric and epi-GaAs layers. The epi-GaAs layer was grown on Ge substrates at 675 °C with and without buffer layer between epi-GaAs layer and Ge substrates. The TiAlO/epi-GaAs interface with an AlGaAs buffer layer allows realizing a high-quality interface between epi-GaAs layers and TiAlO dielectric, much sought after for high-speed transistor applications on a silicon platform. TiAlO dielectric is amorphous even upon annealing at 500 °C and exhibits a sharp interface with epi-GaAs layers. The choice of AlGaAs over AlAs for a buffer layer was made based on the quality of resulting TiAlO/epi-GaAs surface passivation as evident through structural and electrical characteristics. Epi-GaAs with an AlGaAs buffer layer was found to improve the performance of the MOSC significantly through increase in accumulation capacitance and breakdown voltage. The interface state density, flatband voltage, frequency dispersion, and leakage current were decreased for the MOSC fabricated with an AlGaAs buffer layer.
12 citations
Cites background from "Academic and industry research prog..."
...2226243 for p-type MOSFET applications [7]....
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...platform [1]–[4], [7], InAs/GaAs-based quantum-dot laser on Ge [9], and high-efficiency multijunction solar cells [10]....
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TL;DR: In this paper, surface passivation and dislocation management in micro-scale arrays of Ge crystals grown on deeply patterned Si substrates were investigated. And the authors provided compelling information about the competitive interplay between the radiative band-edge transitions and the trapping of carriers by dislocations and free surfaces.
Abstract: We address nonradiative recombination pathways by leveraging surface passivation and dislocation management in μm-scale arrays of Ge crystals grown on deeply patterned Si substrates. The time decay photoluminescence (PL) at cryogenic temperatures discloses carrier lifetimes approaching 45 ns in band-gap engineered Ge micro-crystals. This investigation provides compelling information about the competitive interplay between the radiative band-edge transitions and the trapping of carriers by dislocations and free surfaces. Furthermore, an in-depth analysis of the temperature dependence of the PL, combined with capacitance data and finite difference time domain modeling, demonstrates the effectiveness of GeO2 in passivating the surface of Ge and thus in enhancing the room temperature PL emission.
12 citations
References
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01 Dec 2007
TL;DR: In this paper, a 45 nm logic technology is described that for the first time incorporates high-k + metal gate transistors in a high volume manufacturing process, resulting in the highest drive currents yet reported for NMOS and PMOS.
Abstract: A 45 nm logic technology is described that for the first time incorporates high-k + metal gate transistors in a high volume manufacturing process. The transistors feature 1.0 nm EOT high-k gate dielectric, dual band edge workfunction metal gates and third generation strained silicon, resulting in the highest drive currents yet reported for NMOS and PMOS. The technology also features trench contact based local routing, 9 layers of copper interconnect with low-k ILD, low cost 193 nm dry patterning, and 100% Pb-free packaging. Process yield, performance and reliability are demonstrated on 153 Mb SRAM arrays with SRAM cell size of 0.346 mum2, and on multiple microprocessors.
973 citations
08 Dec 2003
TL;DR: In this article, the authors describe a novel strained transistor architecture which is incorporated into a 90nm logic technology on 300mm wafers, which features an epitaxially grown strained SiGe film embedded in the source drain regions.
Abstract: This paper describes the details of a novel strained transistor architecture which is incorporated into a 90nm logic technology on 300mm wafers The unique strained PMOS transistor structure features an epitaxially grown strained SiGe film embedded in the source drain regions Dramatic performance enhancement relative to unstrained devices are reported These transistors have gate length of 45nm and 50nm for NMOS and PMOS respectively, 12nm physical gate oxide and Ni salicide World record PMOS drive currents of 700/spl mu/A//spl mu/m (high V/sub T/) and 800/spl mu/A//spl mu/m (low V/sub T/) at 12V are demonstrated NMOS devices exercise a highly tensile silicon nitride capping layer to induce tensile strain in the NMOS channel region High NMOS drive currents of 126mA//spl mu/m (high VT) and 145mA//spl mu/m (low VT) at 12V are reported The technology is mature and is being ramped into high volume manufacturing to fabricate next generation Pentium/spl reg/ and Intel/spl reg/ Centrino/spl trade/ processor families
729 citations
TL;DR: In this paper, a method of controlling threading dislocation densities in Ge on Si involving graded SiGe layers and chemical-mechanical polishing (CMP) is presented.
Abstract: A method of controlling threading dislocation densities in Ge on Si involving graded SiGe layers and chemical-mechanical polishing (CMP) is presented. This method has allowed us to grow a relaxed graded buffer to 100% Ge without the increase in threading dislocation density normally observed in thick graded structures. This sample has been characterized by transmission electron microscopy, etch-pit density, atomic force microscopy, Nomarski optical microscopy, and triple-axis x-ray diffraction. Compared to other relaxed graded buffers in which CMP was not implemented, this sample exhibits improvements in threading dislocation density and surface roughness. We have also made process modifications in order to eliminate particles due to gas-phase nucleation and cracks due to thermal mismatch strain. We have achieved relaxed Ge on Si with a threading dislocation density of 2.1×106 cm−2, and we expect that further process refinements will lead to lower threading dislocation densities on the order of bulk Ge su...
620 citations
TL;DR: In this article, the opportunities and challenges of high-k/Ge MOSFETs are discussed on the basis of the material properties of Ge oxide to provide insights for future progress.
443 citations