Academic and industry research progress in germanium nanodevices
TL;DR: Germanium-based transistors have the potential to operate at high speeds with low power requirements and might therefore be used in non-silicon-based semiconductor technology in the future.
Abstract: Silicon has enabled the rise of the semiconductor electronics industry, but it was not the first material used in such devices. During the 1950s, just after the birth of the transistor, solid-state devices were almost exclusively manufactured from germanium. Today, one of the key ways to improve transistor performance is to increase charge-carrier mobility within the device channel. Motivated by this, the solid-state device research community is returning to investigating the high-mobility material germanium. Germanium-based transistors have the potential to operate at high speeds with low power requirements and might therefore be used in non-silicon-based semiconductor technology in the future.
Citations
More filters
TL;DR: In this article, a ribbon bonding with interfaces passivated by an amorphous interlayer was proposed for bulk material heterojunction fabrication, which exhibited rectifying characteristics with a turn-on voltage of 0.3 V and an ideality factor of 2.15.
Abstract: A bonding technique via passivating interlayer formation is proposed for bulk material heterojunction fabrication. n+Si/pGe heterojunctions were fabricated by a ribbon bonding with interfaces passivated by an amorphous interlayer. With a highest process temperature as low as 150 °C, the bonded junctions exhibited rectifying characteristics with a turn-on voltage of 0.3 V as an ideal Si/Ge heterojunction and an ideality factor of 2.15. This technique shows a great potential for bulk material heterojunction formation, especially when ultimately abrupt junctions and low temperature processes are needed.
11 citations
Cites background from "Academic and industry research prog..."
...2% lattice mismatch between Si and Ge, thick SiGe buffer layers and high temperature process via complex reactors have to be used [10]–[18]....
[...]
22 Jan 2021
TL;DR: In this paper, a vertical gate-all-around semiconductor nanowires (p-FETs) based on advanced Ge0.92Sn0.08/Ge group IV epitaxial heterostructures are presented.
Abstract: Harvesting the full potential of single-crystal semiconductor nanowires (NWs) for advanced nanoscale field-effect transistors (FETs) requires a smart combination of charge control architecture and functional semiconductors. In this article, high-performance vertical gate-all-around NW p-type FETs (p-FETs) are presented. The device concept is based on advanced Ge0.92Sn0.08/Ge group IV epitaxial heterostructures, employing quasi–one-dimensional semiconductor NWs fabricated with a top-down approach. The advantage of using a heterostructure is the possibility of electronic band engineering with band offsets tunable by changing the semiconductor stoichiometry and elastic strain. The use of a Ge0.92Sn0.08 layer as the source in GeSn/Ge NW p-FETs results in a small subthreshold slope of 72 mV/dec and a high ION/IOFF ratio of 3 × 106. A ∼32% drive current enhancement is obtained compared to the vertical Ge homojunction NW control devices. More interestingly, the drain-induced barrier lowering is much smaller with GeSn instead of Ge as the source. The general improvement of the transistor’s key figures of merits originates from the valence band offset at the Ge0.92Sn0.08/Ge heterojunction, as well as from a smaller NiGeSn/GeSn contact resistivity.
11 citations
TL;DR: Fabrication of porous, foam-like germanium-based (Ge-based) nanostructures is achieved with the use of the amphiphilic diblock copolymer polystyrene-b-polyethylene oxide as structure directing agent.
Abstract: Fabrication of porous, foam-like germanium-based (Ge-based) nanostructures is achieved with the use of the amphiphilic diblock copolymer polystyrene-b-polyethylene oxide as structure directing agent. Basic concepts of block copolymer assisted sol–gel synthesis are successfully realized based on the [Ge9]4− Zintl clusters as a precursor for Ge-based thin films. Material/elemental composition and crystalline Ge-based phases are investigated via X-ray photoelectron spectroscopy and X-ray diffraction measurements, respectively. Poor-good solvent pair induced phase separation leads to pore sizes in the Ge-based films up to 40 nm, which can be tuned through a change of the molar mixing ratio between polymer template and precursor as proven by grazing incidence small angle X-ray scattering and scanning electron microscopy.
11 citations
TL;DR: In this article, the incorporation of nitrogen into the oxide layer by thermally growing GeOxNy films in NO has been shown to improve the stability of metal-oxide-semiconductor devices.
Abstract: The thermal instability of GeO2/Ge structures lasts as a barrier against the development of Ge-based metal-oxide-semiconductor devices. In the present work, stabilization was achieved through the incorporation of nitrogen into the oxide layer by thermally growing GeOxNy films in NO. With this approach, a stable layer is obtained in a single step as opposed to other nitridation techniques (like plasma immersion) which require additional processing. Significant reduction of GeO desorption from the surface and a strong barrier against additional substrate oxidation were obtained by the insertion of a small amount of nitrogen content (N/O ≈ 10%). Nuclear reaction analysis and profiling showed that nitrogen incorporation and removal occur simultaneously during film growth, yielding N to be distributed throughout the whole film, without accumulation in any particular region. Both the oxidation barrier and the lower GeO desorption rate are explained by a reduction of vacancy diffusivity inside the dielectric. Th...
11 citations
TL;DR: In this article, a highly ordered and damage-free microscale germanium inverted pyramid array fabricated by HF-free metal-assisted chemical etching is presented, demonstrating the good preservation of single crystallinity with a minimized amount of defects at etched surfaces.
Abstract: With increasing demand for infrared (IR) photonics and optoelectronics, germanium (Ge) has recently regained attention due to its outstanding optical properties in the near infrared (NIR) and mid infrared (MIR) ranges. Here we present a highly ordered and damage-free microscale Ge inverted pyramid array fabricated by HF-free metal-assisted chemical etching. The surface quality of the inverted pyramid is systematically investigated, demonstrating the good preservation of single crystallinity with a minimized amount of defects at etched surfaces. In addition, an outstanding antireflection performance of the Ge inverted pyramid is realized in a broadband MIR wavelength range up to 15 μm. The damage-free Ge inverted pyramid array, together with its strong antireflection capability in the MIR range, provides an outstanding platform for future MIR photonic and optoelectronic applications.
11 citations
References
More filters
01 Dec 2007
TL;DR: In this paper, a 45 nm logic technology is described that for the first time incorporates high-k + metal gate transistors in a high volume manufacturing process, resulting in the highest drive currents yet reported for NMOS and PMOS.
Abstract: A 45 nm logic technology is described that for the first time incorporates high-k + metal gate transistors in a high volume manufacturing process. The transistors feature 1.0 nm EOT high-k gate dielectric, dual band edge workfunction metal gates and third generation strained silicon, resulting in the highest drive currents yet reported for NMOS and PMOS. The technology also features trench contact based local routing, 9 layers of copper interconnect with low-k ILD, low cost 193 nm dry patterning, and 100% Pb-free packaging. Process yield, performance and reliability are demonstrated on 153 Mb SRAM arrays with SRAM cell size of 0.346 mum2, and on multiple microprocessors.
973 citations
08 Dec 2003
TL;DR: In this article, the authors describe a novel strained transistor architecture which is incorporated into a 90nm logic technology on 300mm wafers, which features an epitaxially grown strained SiGe film embedded in the source drain regions.
Abstract: This paper describes the details of a novel strained transistor architecture which is incorporated into a 90nm logic technology on 300mm wafers The unique strained PMOS transistor structure features an epitaxially grown strained SiGe film embedded in the source drain regions Dramatic performance enhancement relative to unstrained devices are reported These transistors have gate length of 45nm and 50nm for NMOS and PMOS respectively, 12nm physical gate oxide and Ni salicide World record PMOS drive currents of 700/spl mu/A//spl mu/m (high V/sub T/) and 800/spl mu/A//spl mu/m (low V/sub T/) at 12V are demonstrated NMOS devices exercise a highly tensile silicon nitride capping layer to induce tensile strain in the NMOS channel region High NMOS drive currents of 126mA//spl mu/m (high VT) and 145mA//spl mu/m (low VT) at 12V are reported The technology is mature and is being ramped into high volume manufacturing to fabricate next generation Pentium/spl reg/ and Intel/spl reg/ Centrino/spl trade/ processor families
729 citations
TL;DR: In this paper, a method of controlling threading dislocation densities in Ge on Si involving graded SiGe layers and chemical-mechanical polishing (CMP) is presented.
Abstract: A method of controlling threading dislocation densities in Ge on Si involving graded SiGe layers and chemical-mechanical polishing (CMP) is presented. This method has allowed us to grow a relaxed graded buffer to 100% Ge without the increase in threading dislocation density normally observed in thick graded structures. This sample has been characterized by transmission electron microscopy, etch-pit density, atomic force microscopy, Nomarski optical microscopy, and triple-axis x-ray diffraction. Compared to other relaxed graded buffers in which CMP was not implemented, this sample exhibits improvements in threading dislocation density and surface roughness. We have also made process modifications in order to eliminate particles due to gas-phase nucleation and cracks due to thermal mismatch strain. We have achieved relaxed Ge on Si with a threading dislocation density of 2.1×106 cm−2, and we expect that further process refinements will lead to lower threading dislocation densities on the order of bulk Ge su...
620 citations
TL;DR: In this article, the opportunities and challenges of high-k/Ge MOSFETs are discussed on the basis of the material properties of Ge oxide to provide insights for future progress.
443 citations