Academic and industry research progress in germanium nanodevices
TL;DR: Germanium-based transistors have the potential to operate at high speeds with low power requirements and might therefore be used in non-silicon-based semiconductor technology in the future.
Abstract: Silicon has enabled the rise of the semiconductor electronics industry, but it was not the first material used in such devices. During the 1950s, just after the birth of the transistor, solid-state devices were almost exclusively manufactured from germanium. Today, one of the key ways to improve transistor performance is to increase charge-carrier mobility within the device channel. Motivated by this, the solid-state device research community is returning to investigating the high-mobility material germanium. Germanium-based transistors have the potential to operate at high speeds with low power requirements and might therefore be used in non-silicon-based semiconductor technology in the future.
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TL;DR: In this article, the main mechanisms underlying the defect generation and accumulation during the ion implantation processes were summarized and the damage evolution during post-implantation annealing was treated, with emphasis on agglomerates of intrinsic defects in Si.
Abstract: Defects produced by ion implantation in Si and Ge, their evolution upon post-implantation annealing, and their role in shallow junction formation processes in Si and Ge are reviewed in this chapter. After summarizing the main mechanisms underlying the defect generation and accumulation during the ion implantation processes, the damage evolution during post-implantation annealing will be treated, with emphasis on agglomerates of intrinsic defects in Si. Afterward, anomalous dopant diffusion and electrical activation phenomena occurring in Si and Ge after post-implantation annealing will be treated, with a particular focus on point defect engineering strategies for shallow junction optimization.
9 citations
TL;DR: In this article, the formation of high-quality germanium on oxide for photodetectors as well as its characteristic measurements were reported by using the rapid-melting growth technique, and the quality was verified by Raman spectroscopy and standard electron microscopy.
Abstract: For high-speed data processing, the synergy of photons and electrons requires their absorption and conversion characteristics to be suited for near-infrared optical communication. Here, we report on the formation of high-quality germanium on oxide for photodetectors as well as its characteristic measurements. The Ge film was made by using the rapid-melting-growth technique, and the quality was verified by Raman spectroscopy and standard electron microscopy. The high-quality Ge was integrated with P-type and N-type silicon pillars to form a PIN photodetector. The electrical measurement identified its responsivity to the near-infrared spectrum. This work demonstrated that a high-quality Ge film can be obtained using a metal-oxide-semiconductor field-effect transistor compatible process with good photoelectric conversion efficiency and responsivity.
9 citations
TL;DR: In this article, the semi-conductor Ge0.9Sn0.1 was used for magnetron sputtering to produce low-cost and CMOS-compatible relaxed pseudo-coherent layers with x ≥ 0.1.
Abstract: The semi-conductor Ge1―xSnx exhibits interesting properties for optoelectronic applications. In particular, Ge1―xSnx alloys with x ≥ 0.1 exhibit a direct band-gap, and integrated in complementary-metal-oxide-semiconductor (CMOS) technology, should allow the development of Si photonics. CMOS-compatible magnetron sputtering deposition was shown to produce monocrystalline Ge1―xSnx films with good electrical properties at low cost. However, these layers were grown at low temperature ( 600 K) on Si(001) by magnetron sputtering in order to produce low-cost and CMOS-compatible relaxed pseudo-coherent layers with x ≥ 0.1 exhibiting a better crystallinity. Ge1―xSnx crystallization and Ge1―xSnx crystal growth were investigated. Crystallization of an amorphous Ge1―xSnx layer deposited on Si(001) or Ge(001) grown on Si(001) leads to the growth of polycrystalline films. Furthermore, the competition between Ge/Sn phase separation and Ge1―xSnx growth prevents the formation of large-grain Sn-rich Ge1―xSnx layers without the formation of β-Sn islands on the layer surface, due to significant atomic redistribution kinetics at the crystallization temperature (T = 733 K for x = 0.17). However, the growth at T = 633 K of a highly-relaxed pseudo-coherent Ge0.9Sn0.1 film with low impurity concentrations (
9 citations
TL;DR: In this paper, the effects of post deposition annealing (PDA) atmosphere, including oxygen (O2) gas and forming gas (FG), on interfacial and electrical properties of a HfO2 gate dielectric on nitrided Ge are analyzed.
9 citations
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TL;DR: In this paper, the authors predict that spatially indirect excitons in a lattice-matched strained Si/Ge bilayer embedded into a germanium-rich SiGe crystal, would lead to observable mass-imbalanced electron-hole superfluidity and BEC.
Abstract: Excitons are promising candidates for generating superfluidity and Bose-Einstein Condensation (BEC) in solid state devices, but an enabling material platform with in-built bandstructure advantages and scaling compatibility with industrial semiconductor technology is lacking. Here we predict that spatially indirect excitons in a lattice-matched strained Si/Ge bilayer embedded into a germanium-rich SiGe crystal, would lead to observable mass-imbalanced electron-hole superfluidity and BEC. Holes would be confined in a compressively strained Ge quantum well and electrons in a lattice-matched tensile strained Si quantum well. We envision a device architecture that does not require an insulating barrier at the Si/Ge interface, since this interface offers a type II band alignment. Thus the electrons and holes can be kept very close but strictly separate, strengthening the electron-hole pairing attraction while preventing fast electron-hole recombination. The band alignment also allows a one-step procedure for making independent contacts to the electron and hole layers, overcoming a significant obstacle to device fabrication. We predict superfluidity at experimentally accessible temperatures of a few Kelvin and carrier densities up to $\sim 6\times 10^{10}$ cm$^{-2}$, while the large imbalance of the electron and hole effective masses can lead to exotic superfluid phases.
9 citations
References
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01 Dec 2007
TL;DR: In this paper, a 45 nm logic technology is described that for the first time incorporates high-k + metal gate transistors in a high volume manufacturing process, resulting in the highest drive currents yet reported for NMOS and PMOS.
Abstract: A 45 nm logic technology is described that for the first time incorporates high-k + metal gate transistors in a high volume manufacturing process. The transistors feature 1.0 nm EOT high-k gate dielectric, dual band edge workfunction metal gates and third generation strained silicon, resulting in the highest drive currents yet reported for NMOS and PMOS. The technology also features trench contact based local routing, 9 layers of copper interconnect with low-k ILD, low cost 193 nm dry patterning, and 100% Pb-free packaging. Process yield, performance and reliability are demonstrated on 153 Mb SRAM arrays with SRAM cell size of 0.346 mum2, and on multiple microprocessors.
973 citations
08 Dec 2003
TL;DR: In this article, the authors describe a novel strained transistor architecture which is incorporated into a 90nm logic technology on 300mm wafers, which features an epitaxially grown strained SiGe film embedded in the source drain regions.
Abstract: This paper describes the details of a novel strained transistor architecture which is incorporated into a 90nm logic technology on 300mm wafers The unique strained PMOS transistor structure features an epitaxially grown strained SiGe film embedded in the source drain regions Dramatic performance enhancement relative to unstrained devices are reported These transistors have gate length of 45nm and 50nm for NMOS and PMOS respectively, 12nm physical gate oxide and Ni salicide World record PMOS drive currents of 700/spl mu/A//spl mu/m (high V/sub T/) and 800/spl mu/A//spl mu/m (low V/sub T/) at 12V are demonstrated NMOS devices exercise a highly tensile silicon nitride capping layer to induce tensile strain in the NMOS channel region High NMOS drive currents of 126mA//spl mu/m (high VT) and 145mA//spl mu/m (low VT) at 12V are reported The technology is mature and is being ramped into high volume manufacturing to fabricate next generation Pentium/spl reg/ and Intel/spl reg/ Centrino/spl trade/ processor families
729 citations
TL;DR: In this paper, a method of controlling threading dislocation densities in Ge on Si involving graded SiGe layers and chemical-mechanical polishing (CMP) is presented.
Abstract: A method of controlling threading dislocation densities in Ge on Si involving graded SiGe layers and chemical-mechanical polishing (CMP) is presented. This method has allowed us to grow a relaxed graded buffer to 100% Ge without the increase in threading dislocation density normally observed in thick graded structures. This sample has been characterized by transmission electron microscopy, etch-pit density, atomic force microscopy, Nomarski optical microscopy, and triple-axis x-ray diffraction. Compared to other relaxed graded buffers in which CMP was not implemented, this sample exhibits improvements in threading dislocation density and surface roughness. We have also made process modifications in order to eliminate particles due to gas-phase nucleation and cracks due to thermal mismatch strain. We have achieved relaxed Ge on Si with a threading dislocation density of 2.1×106 cm−2, and we expect that further process refinements will lead to lower threading dislocation densities on the order of bulk Ge su...
620 citations
TL;DR: In this article, the opportunities and challenges of high-k/Ge MOSFETs are discussed on the basis of the material properties of Ge oxide to provide insights for future progress.
443 citations