Academic and industry research progress in germanium nanodevices
TL;DR: Germanium-based transistors have the potential to operate at high speeds with low power requirements and might therefore be used in non-silicon-based semiconductor technology in the future.
Abstract: Silicon has enabled the rise of the semiconductor electronics industry, but it was not the first material used in such devices. During the 1950s, just after the birth of the transistor, solid-state devices were almost exclusively manufactured from germanium. Today, one of the key ways to improve transistor performance is to increase charge-carrier mobility within the device channel. Motivated by this, the solid-state device research community is returning to investigating the high-mobility material germanium. Germanium-based transistors have the potential to operate at high speeds with low power requirements and might therefore be used in non-silicon-based semiconductor technology in the future.
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TL;DR: In this paper, the channel width scaling of back-gated MoS2 field effect transistors from 2 μm down to 60 nm was studied. And the authors showed that the channel conductance scales linearly with channel width, indicating no evident edge damage for MoS 2 nanoribbons with widths down to 50 nm as defined by plasma dry etching.
Abstract: We study the channel width scaling of back-gated MoS2 metal-oxide-semiconductor field-effect transistors from 2 μm down to 60 nm. We reveal that the channel conductance scales linearly with channel width, indicating no evident edge damage for MoS2 nanoribbons with widths down to 60 nm as defined by plasma dry etching. However, these transistors show a strong positive threshold voltage (VT) shift with narrow channel widths of less than 200 nm. Our results also show that transistors with thinner channel thicknesses have larger VT shifts associated with width scaling. Devices fabricated on a 6-nm-thick MoS2 crystal underwent the transition from depletion mode to enhancement mode.
101 citations
TL;DR: A low temperature nickel process has been developed that produces Ohmic contacts to n-type germanium with specific contact resistivities down to (23 −± 18) −7 Ω-cm2 for anneal temperatures of 340 −°C.
Abstract: A low temperature nickel process has been developed that produces Ohmic contacts to n-type germanium with specific contact resistivities down to (23 ± 18) × 10−7 Ω-cm2 for anneal temperatures of 340 °C The low contact resistivity is attributed to the low resistivity NiGe phase which was identified using electron diffraction in a transmission electron microscope Electrical results indicate that the linear Ohmic behaviour of the contact is attributed to quantum mechanical tunnelling through the Schottky barrier formed between the NiGe alloy and the heavily doped n-Ge
97 citations
TL;DR: In this paper, a 2D hole gas of high mobility (5 × 105 cm2 V−1 s−1) is demonstrated in a very shallow strained germanium (Ge) channel, which is located only 22 nm below the surface.
Abstract: Buried-channel semiconductor heterostructures are an archetype material platform for the fabrication of gated semiconductor quantum devices. Sharp confinement potential is obtained by positioning the channel near the surface; however, nearby surface states degrade the electrical properties of the starting material. Here, a 2D hole gas of high mobility (5 × 105 cm2 V−1 s−1) is demonstrated in a very shallow strained germanium (Ge) channel, which is located only 22 nm below the surface. The top-gate of a dopant-less field effect transistor controls the channel carrier density confined in an undoped Ge/SiGe heterostructure with reduced background contamination, sharp interfaces, and high uniformity. The high mobility leads to mean free paths ≈ 6 µm, setting new benchmarks for holes in shallow field effect transistors. The high mobility, along with a percolation density of 1.2 × 1011cm−2, light effective mass (0.09me), and high effective g-factor (up to 9.2) highlight the potential of undoped Ge/SiGe as a low-disorder material platform for hybrid quantum technologies.
86 citations
TL;DR: In this article, a review of the many groups that have used atomic layer deposition (ALD) for the conformal deposition of oxide thin films with nanoscale thickness control is presented.
Abstract: Atomic layer deposition (ALD) is a proven technique for the conformal deposition of oxide thin films with nanoscale thickness control. Most successful industrial applications have been with binary oxides, such as Al2O3 and HfO2. However, there has been much effort to deposit ternary oxides, such as perovskites (ABO3), with desirable properties for advanced thin film applications. Distinct challenges are presented by the deposition of multi-component oxides using ALD. This review is intended to highlight the research of the many groups that have deposited perovskite oxides by ALD methods. Several commonalities between the studies are discussed. Special emphasis is put on precursor selection, deposition temperatures, and specific property performance (high-k, ferroelectric, ferromagnetic, etc.). Finally, the monolithic integration of perovskite oxides with semiconductors by ALD is reviewed. High-quality epitaxial growth of oxide thin films has traditionally been limited to physical vapor deposition techniques (e.g., molecular beam epitaxy). However, recent studies have demonstrated that epitaxial oxide thin films may be deposited on semiconductor substrates using ALD. This presents an exciting opportunity to integrate functional perovskite oxides for advanced semiconductor applications in a process that is economical and scalable.
79 citations
TL;DR: This work demonstrates wafer-scale integration of vertical field-effect transistors (VFETs) based on graphene-In-Ga-Zn-O (IGZO)-metal asymmetric junctions on a transparent 150 × 150 mm(2) glass and designs a triangular energy barrier between the graphene and metal.
Abstract: Graphene heterostructures in which graphene is combined with semiconductors or other layered 2D materials are of considerable interest, as a new class of electronic devices has been realized. Here we propose a technology platform based on graphene-thin-film-semiconductor-metal (GSM) junctions, which can be applied to large-scale and power-efficient electronics compatible with a variety of substrates. We demonstrate wafer-scale integration of vertical field-effect transistors (VFETs) based on graphene-In-Ga-Zn-O (IGZO)-metal asymmetric junctions on a transparent 150 × 150 mm(2) glass. In this system, a triangular energy barrier between the graphene and metal is designed by selecting a metal with a proper work function. We obtain a maximum current on/off ratio (Ion/Ioff) up to 10(6) with an average of 3010 over 2000 devices under ambient conditions. For low-power logic applications, an inverter that combines complementary n-type (IGZO) and p-type (Ge) devices is demonstrated to operate at a bias of only 0.5 V.
76 citations
References
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01 Dec 2007
TL;DR: In this paper, a 45 nm logic technology is described that for the first time incorporates high-k + metal gate transistors in a high volume manufacturing process, resulting in the highest drive currents yet reported for NMOS and PMOS.
Abstract: A 45 nm logic technology is described that for the first time incorporates high-k + metal gate transistors in a high volume manufacturing process. The transistors feature 1.0 nm EOT high-k gate dielectric, dual band edge workfunction metal gates and third generation strained silicon, resulting in the highest drive currents yet reported for NMOS and PMOS. The technology also features trench contact based local routing, 9 layers of copper interconnect with low-k ILD, low cost 193 nm dry patterning, and 100% Pb-free packaging. Process yield, performance and reliability are demonstrated on 153 Mb SRAM arrays with SRAM cell size of 0.346 mum2, and on multiple microprocessors.
973 citations
08 Dec 2003
TL;DR: In this article, the authors describe a novel strained transistor architecture which is incorporated into a 90nm logic technology on 300mm wafers, which features an epitaxially grown strained SiGe film embedded in the source drain regions.
Abstract: This paper describes the details of a novel strained transistor architecture which is incorporated into a 90nm logic technology on 300mm wafers The unique strained PMOS transistor structure features an epitaxially grown strained SiGe film embedded in the source drain regions Dramatic performance enhancement relative to unstrained devices are reported These transistors have gate length of 45nm and 50nm for NMOS and PMOS respectively, 12nm physical gate oxide and Ni salicide World record PMOS drive currents of 700/spl mu/A//spl mu/m (high V/sub T/) and 800/spl mu/A//spl mu/m (low V/sub T/) at 12V are demonstrated NMOS devices exercise a highly tensile silicon nitride capping layer to induce tensile strain in the NMOS channel region High NMOS drive currents of 126mA//spl mu/m (high VT) and 145mA//spl mu/m (low VT) at 12V are reported The technology is mature and is being ramped into high volume manufacturing to fabricate next generation Pentium/spl reg/ and Intel/spl reg/ Centrino/spl trade/ processor families
729 citations
TL;DR: In this paper, a method of controlling threading dislocation densities in Ge on Si involving graded SiGe layers and chemical-mechanical polishing (CMP) is presented.
Abstract: A method of controlling threading dislocation densities in Ge on Si involving graded SiGe layers and chemical-mechanical polishing (CMP) is presented. This method has allowed us to grow a relaxed graded buffer to 100% Ge without the increase in threading dislocation density normally observed in thick graded structures. This sample has been characterized by transmission electron microscopy, etch-pit density, atomic force microscopy, Nomarski optical microscopy, and triple-axis x-ray diffraction. Compared to other relaxed graded buffers in which CMP was not implemented, this sample exhibits improvements in threading dislocation density and surface roughness. We have also made process modifications in order to eliminate particles due to gas-phase nucleation and cracks due to thermal mismatch strain. We have achieved relaxed Ge on Si with a threading dislocation density of 2.1×106 cm−2, and we expect that further process refinements will lead to lower threading dislocation densities on the order of bulk Ge su...
620 citations
TL;DR: In this article, the opportunities and challenges of high-k/Ge MOSFETs are discussed on the basis of the material properties of Ge oxide to provide insights for future progress.
443 citations