Academic and industry research progress in germanium nanodevices
TL;DR: Germanium-based transistors have the potential to operate at high speeds with low power requirements and might therefore be used in non-silicon-based semiconductor technology in the future.
Abstract: Silicon has enabled the rise of the semiconductor electronics industry, but it was not the first material used in such devices. During the 1950s, just after the birth of the transistor, solid-state devices were almost exclusively manufactured from germanium. Today, one of the key ways to improve transistor performance is to increase charge-carrier mobility within the device channel. Motivated by this, the solid-state device research community is returning to investigating the high-mobility material germanium. Germanium-based transistors have the potential to operate at high speeds with low power requirements and might therefore be used in non-silicon-based semiconductor technology in the future.
Citations
More filters
TL;DR: In this article, the thermal conductivity of amorphous alumina films with a density of 277 ± 1.4 cm − 3 is measured to be 173 ± 008 ǫ w 0.
Abstract: Sub-nanometer thickness accuracy and excellent conformity make atomic layer deposited films prevalent in modern electronics, continuously shrinking in size The thermal resistance of these films plays a major role in the overall energy efficiency of miniaturized devices We report very sensitive thermal conductivity measurements of amorphous Al 2O 3 thin films grown using atomic layer deposition in the temperature range of 100–300 K The 3 ω method is used to characterize these films ranging from 170 to 1194 nm in thickness, using a series-resistor model to deconvolve the intrinsic thermal conductivity of the film from thermal boundary resistances inherently present in the multilayer system The thermal conductivity of amorphous alumina films with a density of 277 ± 014 g cm − 3 is measured to be 173 ± 008 W m − 1 K − 1 at 300 K Measurements were carried out on germanium and sapphire substrates, leading to no substrate dependence of the films’ thermal conductivity, within experimental accuracy On the other hand, thermal boundary resistances of the systems Pt/Al 2O 3/substrate are observed to be strongly substrate-dependent, with values ranging from 21 × 10 − 8 m 2 K W − 1 to 37 × 10 − 8 m 2 K W − 1 at 300 K for films deposited on sapphire and germanium, respectively These results provide further insights into the significance of interfaces in thermal transport across layered materials, in particular, for potential germanium-based devices
8 citations
TL;DR: The global minima of both neutral and anionic clusters of VGe3-/0 were determined using different quantum chemical methods using DFT, RCCSD(T), CASSCF/CASPT2 and Franck-Condon factor simulations of the first band were performed to obtain more insights into the experimental bands of the spectrum.
Abstract: The global minima of both neutral and anionic clusters of VGe3–/0 were determined using different quantum chemical methods (DFT, RCCSD(T), CASSCF/CASPT2). On the basis of the ground states identified, most excited bands in the anion photoelectron spectrum of VGe3– were assigned. The tetrahedral isomers of both charged states are the most stable ones. A singlet state (Cs , 1A′) of the tetrahedral isomer has the globally lowest energy on the potential hypersurface of VGe3–. Two states 12A′ and 12A″ of the neutral tetrahedral isomer are nearly degenerate and identified as the competing ground state of VGe3. From the anionic ground state, four of five bands in the anion photoelectron spectrum of VGe3– were determined to be the consequences of one-electron transitions starting from the anionic ground state 1A′. Both nearly degenerate neutral ground states are responsible for generation of the first band. Two different transitions from the anionic ground state 1A′ to the first two nearly degenerate excited stat...
8 citations
TL;DR: Germanium/silicon systems are among the most promising materials for development of current semiconductor electronics and photonics as discussed by the authors, and they are very inter-intersecting materials.
Abstract: Germanium/silicon systems are among the most promising materials for development of current semiconductor electronics and photonics. Structures with germanium quantum dots on silicon are very inter...
8 citations
TL;DR: In this article, the relative refractive index (r.i.) ( n r ) of the GeO2 was calculated as 1.8 and the temperature dependent current (I) −voltage (V) characteristics and photocurrent of the Au/GeO2/p-Si Schottky device predicted the tunnelling of the carriers, presence of oxygen defects at the junction.
8 citations
TL;DR: In this paper, the process of electrochemical etching of n-Ge(100) surfaces was studied for aqueous HCl solutions by voltammetry, atomic force and scanning electron microscopy, reflectance measurements and X-ray photoelectron spectroscopy.
Abstract: The process of electrochemical etching of n-Ge(100) surfaces was studied for aqueous HCl solutions by voltammetry, atomic force and scanning electron microscopy, reflectance measurements and X-ray photoelectron spectroscopy. Under applied potential conditions, unexpected random pyramid texturization was observed for the high HCl concentration range evidenced by the formation of characteristic (111) facets. The morphological changes were accompanied by a photocurrent enhancement and a decreased reflectance. By patterning the pyramids, a high structure density could be achieved. The resulting decrease of the reflectance indicates that the coupling of light into the semiconductor was improved. Integrated electrochemical X-ray photoelectron spectroscopy measurements allowed us to relate surface chlorination to the obtained morphological features. Photoanodic etching schemes are presented to provide insight into these striking results.
8 citations
References
More filters
01 Dec 2007
TL;DR: In this paper, a 45 nm logic technology is described that for the first time incorporates high-k + metal gate transistors in a high volume manufacturing process, resulting in the highest drive currents yet reported for NMOS and PMOS.
Abstract: A 45 nm logic technology is described that for the first time incorporates high-k + metal gate transistors in a high volume manufacturing process. The transistors feature 1.0 nm EOT high-k gate dielectric, dual band edge workfunction metal gates and third generation strained silicon, resulting in the highest drive currents yet reported for NMOS and PMOS. The technology also features trench contact based local routing, 9 layers of copper interconnect with low-k ILD, low cost 193 nm dry patterning, and 100% Pb-free packaging. Process yield, performance and reliability are demonstrated on 153 Mb SRAM arrays with SRAM cell size of 0.346 mum2, and on multiple microprocessors.
973 citations
08 Dec 2003
TL;DR: In this article, the authors describe a novel strained transistor architecture which is incorporated into a 90nm logic technology on 300mm wafers, which features an epitaxially grown strained SiGe film embedded in the source drain regions.
Abstract: This paper describes the details of a novel strained transistor architecture which is incorporated into a 90nm logic technology on 300mm wafers The unique strained PMOS transistor structure features an epitaxially grown strained SiGe film embedded in the source drain regions Dramatic performance enhancement relative to unstrained devices are reported These transistors have gate length of 45nm and 50nm for NMOS and PMOS respectively, 12nm physical gate oxide and Ni salicide World record PMOS drive currents of 700/spl mu/A//spl mu/m (high V/sub T/) and 800/spl mu/A//spl mu/m (low V/sub T/) at 12V are demonstrated NMOS devices exercise a highly tensile silicon nitride capping layer to induce tensile strain in the NMOS channel region High NMOS drive currents of 126mA//spl mu/m (high VT) and 145mA//spl mu/m (low VT) at 12V are reported The technology is mature and is being ramped into high volume manufacturing to fabricate next generation Pentium/spl reg/ and Intel/spl reg/ Centrino/spl trade/ processor families
729 citations
TL;DR: In this paper, a method of controlling threading dislocation densities in Ge on Si involving graded SiGe layers and chemical-mechanical polishing (CMP) is presented.
Abstract: A method of controlling threading dislocation densities in Ge on Si involving graded SiGe layers and chemical-mechanical polishing (CMP) is presented. This method has allowed us to grow a relaxed graded buffer to 100% Ge without the increase in threading dislocation density normally observed in thick graded structures. This sample has been characterized by transmission electron microscopy, etch-pit density, atomic force microscopy, Nomarski optical microscopy, and triple-axis x-ray diffraction. Compared to other relaxed graded buffers in which CMP was not implemented, this sample exhibits improvements in threading dislocation density and surface roughness. We have also made process modifications in order to eliminate particles due to gas-phase nucleation and cracks due to thermal mismatch strain. We have achieved relaxed Ge on Si with a threading dislocation density of 2.1×106 cm−2, and we expect that further process refinements will lead to lower threading dislocation densities on the order of bulk Ge su...
620 citations
TL;DR: In this article, the opportunities and challenges of high-k/Ge MOSFETs are discussed on the basis of the material properties of Ge oxide to provide insights for future progress.
443 citations