Academic and industry research progress in germanium nanodevices
TL;DR: Germanium-based transistors have the potential to operate at high speeds with low power requirements and might therefore be used in non-silicon-based semiconductor technology in the future.
Abstract: Silicon has enabled the rise of the semiconductor electronics industry, but it was not the first material used in such devices. During the 1950s, just after the birth of the transistor, solid-state devices were almost exclusively manufactured from germanium. Today, one of the key ways to improve transistor performance is to increase charge-carrier mobility within the device channel. Motivated by this, the solid-state device research community is returning to investigating the high-mobility material germanium. Germanium-based transistors have the potential to operate at high speeds with low power requirements and might therefore be used in non-silicon-based semiconductor technology in the future.
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TL;DR: In this article , a chalcogenide substitution reaction (CSR) of MoTe2 with lattice inheritance was proposed for the fabrication of highly strained MoS2/MoTe2.
8 citations
TL;DR: In this paper, the authors present quantum transport simulation results for double-gate MOSFETs by using an atomistic full-band basis to evaluate the tunneling currents in the OFF state.
Abstract: We present quantum transport simulation results for InAs and In
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Ga
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As double-gate MOSFETs by using an atomistic full-band basis to evaluate the tunneling currents in the OFF state. While InAs has the advantage of lower mass and higher injection velocity, it also has lower bandgap. For low gate bias, the overlap in energy of the valence band in the channel with the source/drain conduction bands results in band-to-band tunneling (BTBT) between source and drain, which clamps the OFF current. Such current can be reduced by increasing the bandgap of the material either by increasing confinement or by lowering the In content, for example, using In
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Ga
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As. Grading the doping of the source/drain region to create a wider barrier also reduces BTBT, but to a lesser extent.
8 citations
TL;DR: In this article, the impact of H2 high pressure annealing (H2-HPA) on a Y-doped ZrO2/GeOx/Ge gate stack was reported.
Abstract: We report on the impact of H2 high pressure annealing (H2-HPA) on a Y-doped ZrO2 (Y-ZrO2)/GeOx/Ge gate stack. In this paper, compared to conventional forming gas annealing (FGA), the H2-HPA increased the k-value of the Y-doped ZrO2 gate dielectric to as high as 47.8 by enhancing the crystallization of the Y-ZrO2. This process can achieve an aggressively scaled equivalent oxide thickness (EOT) of 0.57 nm with an extremely low gate leakage current (Jg) of $ {4.5} \times {10}^{- {6}}$ A/cm2. In addition, the H2-HPA effectively passivated the dangling bonds and reduced the interface trap density (Dit) to as low as ${3.4} \times {10}^{ {11}}$ eV−1cm−2. The Ge pMOSFETs of the Y-ZrO2 with H2-HPA led to a ~ 70% improvement in the effective hole mobility compared to the counterpart device with the conventional FGA. The device with H2-HPA also showed an improved subthreshold swing (SS) value of 93 mV/dec compared to that with the FGA (135 mV/dec).
8 citations
Dissertation•
01 Jan 2015
TL;DR: In this article, the design and fabrication of Ge/SiGe QCSE devices with thin barrier barriers was presented as a potential way to produce a more energy efficient modulator for optical communications.
Abstract: Silicon photonics technologies have the potential to overcome the bandwidth limitations inherent in electrical interconnect technology. Modulation technology which is efficient both in terms of size and energy is required if silicon photonics are to replace electronics for interconnect communications. Silicon germanium technologies have the potential to not only improve the performance of current semiconductor devices but to also extend the reach of semiconductor technology into new areas such as development of a room temperature THz laser. A novel process that allows easy fabrication of Ohmic contacts to moderately doped n-type Germanium has been developed. This process has the potential to allow the realization of new devices which have been previously hampered by non-Ohmic contacts or dopant segregation problems. This work reported in this thesis also includes the design and fabrication of Ge/SiGe QCSE devices. Thin barrier QCSE designs have been put forward as a potential way to produce a more energy efficient modulator. Simulations of the devices show that a design with 16 nm Ge QWs and 8 nm SiGe barriers can provide effective modulation covering the entire optical communications C band with less than 3 V DC offset and achieve a contrast ratio across the band of over 3 dB. It was also shown that despite the thin barriers the wavefunctions remain well confined to the QWs suggesting that even thinner barriers are possible. MQW structures with thin barriers were grown and photodiodes fabricated from them. While the wafers did not have barriers as thin as designed they were thinner than devices previously demonstrated. From photocurrent measurements it was shown that these MQW structures were able to effectively modulate light near the 1550 nm wavelength with better performance than devices found in the literature.
8 citations
Cites background from "Academic and industry research prog..."
...Ge is an attractive material for use in many different technologies including end-of-roadmap complementary metal-oxide semiconductor (CMOS), where its higher carrier mobilities compared to Si would potentially allow for reduced power operation[85]....
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References
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01 Dec 2007
TL;DR: In this paper, a 45 nm logic technology is described that for the first time incorporates high-k + metal gate transistors in a high volume manufacturing process, resulting in the highest drive currents yet reported for NMOS and PMOS.
Abstract: A 45 nm logic technology is described that for the first time incorporates high-k + metal gate transistors in a high volume manufacturing process. The transistors feature 1.0 nm EOT high-k gate dielectric, dual band edge workfunction metal gates and third generation strained silicon, resulting in the highest drive currents yet reported for NMOS and PMOS. The technology also features trench contact based local routing, 9 layers of copper interconnect with low-k ILD, low cost 193 nm dry patterning, and 100% Pb-free packaging. Process yield, performance and reliability are demonstrated on 153 Mb SRAM arrays with SRAM cell size of 0.346 mum2, and on multiple microprocessors.
973 citations
08 Dec 2003
TL;DR: In this article, the authors describe a novel strained transistor architecture which is incorporated into a 90nm logic technology on 300mm wafers, which features an epitaxially grown strained SiGe film embedded in the source drain regions.
Abstract: This paper describes the details of a novel strained transistor architecture which is incorporated into a 90nm logic technology on 300mm wafers The unique strained PMOS transistor structure features an epitaxially grown strained SiGe film embedded in the source drain regions Dramatic performance enhancement relative to unstrained devices are reported These transistors have gate length of 45nm and 50nm for NMOS and PMOS respectively, 12nm physical gate oxide and Ni salicide World record PMOS drive currents of 700/spl mu/A//spl mu/m (high V/sub T/) and 800/spl mu/A//spl mu/m (low V/sub T/) at 12V are demonstrated NMOS devices exercise a highly tensile silicon nitride capping layer to induce tensile strain in the NMOS channel region High NMOS drive currents of 126mA//spl mu/m (high VT) and 145mA//spl mu/m (low VT) at 12V are reported The technology is mature and is being ramped into high volume manufacturing to fabricate next generation Pentium/spl reg/ and Intel/spl reg/ Centrino/spl trade/ processor families
729 citations
TL;DR: In this paper, a method of controlling threading dislocation densities in Ge on Si involving graded SiGe layers and chemical-mechanical polishing (CMP) is presented.
Abstract: A method of controlling threading dislocation densities in Ge on Si involving graded SiGe layers and chemical-mechanical polishing (CMP) is presented. This method has allowed us to grow a relaxed graded buffer to 100% Ge without the increase in threading dislocation density normally observed in thick graded structures. This sample has been characterized by transmission electron microscopy, etch-pit density, atomic force microscopy, Nomarski optical microscopy, and triple-axis x-ray diffraction. Compared to other relaxed graded buffers in which CMP was not implemented, this sample exhibits improvements in threading dislocation density and surface roughness. We have also made process modifications in order to eliminate particles due to gas-phase nucleation and cracks due to thermal mismatch strain. We have achieved relaxed Ge on Si with a threading dislocation density of 2.1×106 cm−2, and we expect that further process refinements will lead to lower threading dislocation densities on the order of bulk Ge su...
620 citations
TL;DR: In this article, the opportunities and challenges of high-k/Ge MOSFETs are discussed on the basis of the material properties of Ge oxide to provide insights for future progress.
443 citations