Academic and industry research progress in germanium nanodevices
TL;DR: Germanium-based transistors have the potential to operate at high speeds with low power requirements and might therefore be used in non-silicon-based semiconductor technology in the future.
Abstract: Silicon has enabled the rise of the semiconductor electronics industry, but it was not the first material used in such devices. During the 1950s, just after the birth of the transistor, solid-state devices were almost exclusively manufactured from germanium. Today, one of the key ways to improve transistor performance is to increase charge-carrier mobility within the device channel. Motivated by this, the solid-state device research community is returning to investigating the high-mobility material germanium. Germanium-based transistors have the potential to operate at high speeds with low power requirements and might therefore be used in non-silicon-based semiconductor technology in the future.
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TL;DR: In this article , a strained Ge quantum well, grown on a SiGe/Si virtual substrate and hosting two electrostatically defined hole spin qubits, is investigated by synchrotron-based scanning X-ray diffraction microscopy to determine all its Bravais lattice parameters.
Abstract: A strained Ge quantum well, grown on a SiGe/Si virtual substrate and hosting two electrostatically defined hole spin qubits, is nondestructively investigated by synchrotron-based scanning X-ray diffraction microscopy to determine all its Bravais lattice parameters. This allows rendering the three-dimensional spatial dependence of the six strain tensor components with a lateral resolution of approximately 50 nm. Two different spatial scales governing the strain field fluctuations in proximity of the qubits are observed at <100 nm and >1 μm, respectively. The short-ranged fluctuations have a typical bandwidth of 2 × 10–4 and can be quantitatively linked to the compressive stressing action of the metal electrodes defining the qubits. By finite element mechanical simulations, it is estimated that this strain fluctuation is increased up to 6 × 10–4 at cryogenic temperature. The longer-ranged fluctuations are of the 10–3 order and are associated with misfit dislocations in the plastically relaxed virtual substrate. From this, energy variations of the light and heavy-hole energy maxima of the order of several 100 μeV and 1 meV are calculated for electrodes and dislocations, respectively. These insights over material-related inhomogeneities may feed into further modeling for optimization and design of large-scale quantum processors manufactured using the mainstream Si-based microelectronics technology.
7 citations
TL;DR: In this article, an amorphous 3-nm SZO layer was grown from strontium bis(triisopropylcyclopentadienyl), tetrakis (dimethylamido) zirconium, and water at 225°C.
Abstract: Heteroepitaxial growth of crystalline SrZrO3 (SZO) on Ge (001) by atomic layer deposition is reported. Ge (001) surfaces are pretreated with 0.5-monolayers (ML) of Ba and an amorphous ∼3-nm SZO layer is grown from strontium bis(triisopropylcyclopentadienyl), tetrakis (dimethylamido) zirconium, and water at 225 °C. This ∼3-nm layer crystallizes at 590 °C and subsequent SZO growth at 225 °C leads to crystalline films that do not require further annealing. The film properties are investigated using X-ray photoelectron spectroscopy, x-ray diffraction, aberration-corrected electron microscopy, and capacitance-voltage measurements of metal-oxide semiconductor capacitor structures. Capacitance-voltage measurements of the SrZrO3/Ge heterojunctions reveal a dielectric constant of 30 for SrZrO3 and a leakage current density of 2.1 × 10−8 A/cm2 at 1 MV/cm with an equivalent oxide thickness of 0.8 nm. Oxygen plasma pretreatment of Ge (001), Zintl layer formation with 0.5 ML Ba, and atomic deuterium post-growth treatment were explored to lower interface trap density (Dit) and achieved a Dit of 8.56 × 1011 cm−2 eV−1.
7 citations
7 citations
25 Jun 2019
TL;DR: Graphene grown directly on Ge via chemical vapor deposition (CVD) can passivate the underlying Ge surface, preventing its oxidation in ambient air for at least months.
Abstract: Graphene grown directly on Ge via chemical vapor deposition (CVD) can passivate the underlying Ge surface, preventing its oxidation in ambient air for at least months. However, the factors that gov...
7 citations
TL;DR: A first demonstration of the single-atom transistor operating in the quasi-solid-state is given, allowing bistable switching between zero and quantized conductance levels, which are integer multiples of the conductance quantum G0 = 2e2 /h.
Abstract: The single-atom transistor represents a quantum electronic device at room temperature, allowing the switching of an electric current by the controlled and reversible relocation of one single atom within a metallic quantum point contact. So far, the device operates by applying a small voltage to a control electrode or "gate" within the aqueous electrolyte. Here, the operation of the atomic device in the quasi-solid state is demonstrated. Gelation of pyrogenic silica transforms the electrolyte into the quasi-solid state, exhibiting the cohesive properties of a solid and the diffusive properties of a liquid, preventing the leakage problem and avoiding the handling of a liquid system. The electrolyte is characterized by cyclic voltammetry, conductivity measurements, and rotation viscometry. Thus, a first demonstration of the single-atom transistor operating in the quasi-solid-state is given. The silver single-atom and atomic-scale transistors in the quasi-solid-state allow bistable switching between zero and quantized conductance levels, which are integer multiples of the conductance quantum G0 = 2e2 /h. Source-drain currents ranging from 1 to 8 µA are applied in these experiments. Any obvious influence of the gelation of the aqueous electrolyte on the electron transport within the quantum point contact is not observed.
7 citations
References
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01 Dec 2007
TL;DR: In this paper, a 45 nm logic technology is described that for the first time incorporates high-k + metal gate transistors in a high volume manufacturing process, resulting in the highest drive currents yet reported for NMOS and PMOS.
Abstract: A 45 nm logic technology is described that for the first time incorporates high-k + metal gate transistors in a high volume manufacturing process. The transistors feature 1.0 nm EOT high-k gate dielectric, dual band edge workfunction metal gates and third generation strained silicon, resulting in the highest drive currents yet reported for NMOS and PMOS. The technology also features trench contact based local routing, 9 layers of copper interconnect with low-k ILD, low cost 193 nm dry patterning, and 100% Pb-free packaging. Process yield, performance and reliability are demonstrated on 153 Mb SRAM arrays with SRAM cell size of 0.346 mum2, and on multiple microprocessors.
973 citations
08 Dec 2003
TL;DR: In this article, the authors describe a novel strained transistor architecture which is incorporated into a 90nm logic technology on 300mm wafers, which features an epitaxially grown strained SiGe film embedded in the source drain regions.
Abstract: This paper describes the details of a novel strained transistor architecture which is incorporated into a 90nm logic technology on 300mm wafers The unique strained PMOS transistor structure features an epitaxially grown strained SiGe film embedded in the source drain regions Dramatic performance enhancement relative to unstrained devices are reported These transistors have gate length of 45nm and 50nm for NMOS and PMOS respectively, 12nm physical gate oxide and Ni salicide World record PMOS drive currents of 700/spl mu/A//spl mu/m (high V/sub T/) and 800/spl mu/A//spl mu/m (low V/sub T/) at 12V are demonstrated NMOS devices exercise a highly tensile silicon nitride capping layer to induce tensile strain in the NMOS channel region High NMOS drive currents of 126mA//spl mu/m (high VT) and 145mA//spl mu/m (low VT) at 12V are reported The technology is mature and is being ramped into high volume manufacturing to fabricate next generation Pentium/spl reg/ and Intel/spl reg/ Centrino/spl trade/ processor families
729 citations
TL;DR: In this paper, a method of controlling threading dislocation densities in Ge on Si involving graded SiGe layers and chemical-mechanical polishing (CMP) is presented.
Abstract: A method of controlling threading dislocation densities in Ge on Si involving graded SiGe layers and chemical-mechanical polishing (CMP) is presented. This method has allowed us to grow a relaxed graded buffer to 100% Ge without the increase in threading dislocation density normally observed in thick graded structures. This sample has been characterized by transmission electron microscopy, etch-pit density, atomic force microscopy, Nomarski optical microscopy, and triple-axis x-ray diffraction. Compared to other relaxed graded buffers in which CMP was not implemented, this sample exhibits improvements in threading dislocation density and surface roughness. We have also made process modifications in order to eliminate particles due to gas-phase nucleation and cracks due to thermal mismatch strain. We have achieved relaxed Ge on Si with a threading dislocation density of 2.1×106 cm−2, and we expect that further process refinements will lead to lower threading dislocation densities on the order of bulk Ge su...
620 citations
TL;DR: In this article, the opportunities and challenges of high-k/Ge MOSFETs are discussed on the basis of the material properties of Ge oxide to provide insights for future progress.
443 citations