Journal ArticleDOI
Academic and industry research progress in germanium nanodevices
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TLDR
Germanium-based transistors have the potential to operate at high speeds with low power requirements and might therefore be used in non-silicon-based semiconductor technology in the future.Abstract:
Silicon has enabled the rise of the semiconductor electronics industry, but it was not the first material used in such devices. During the 1950s, just after the birth of the transistor, solid-state devices were almost exclusively manufactured from germanium. Today, one of the key ways to improve transistor performance is to increase charge-carrier mobility within the device channel. Motivated by this, the solid-state device research community is returning to investigating the high-mobility material germanium. Germanium-based transistors have the potential to operate at high speeds with low power requirements and might therefore be used in non-silicon-based semiconductor technology in the future.read more
Citations
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Journal ArticleDOI
Materials Science Challenges to Graphene Nanoribbon Electronics.
TL;DR: Graphene nanoribbons (GNRs) have recently emerged as promising candidates for channel materials in future nanoelectronic devices due to their exceptional electronic, thermal, and mechanical properties and chemical inertness.
Journal ArticleDOI
Carrier density modulation in a germanium heterostructure by ferroelectric switching
Patrick Ponath,Kurt Fredrickson,Agham-Bayan S Posadas,Yuan Ren,Xiaoyu Wu,Rama K. Vasudevan,M. Baris Okatan,Stephen Jesse,Toshihiro Aoki,Martha R. McCartney,David J. Smith,Sergei V. Kalinin,Keji Lai,Alexander A. Demkov +13 more
TL;DR: A true ferro electric field effect-carrier density modulation in an underlying Ge(001) substrate is reported by switching of the ferroelectric polarization in epitaxial c-axis-oriented BaTiO3 grown by molecular beam epitaxy.
Journal ArticleDOI
Germanium p-Channel FinFET Fabricated by Aspect Ratio Trapping
Mark J. H. van Dal,Georgios Vellianitis,Blandine Duriez,Gerben Doornbos,C. H. Hsieh,Bi-Hui Lee,Kai-Min Yin,Matthias Passlack,Carlos H. Diaz +8 more
TL;DR: In this article, scaled Ge p-channel FinFETs fabricated on a 300mm Si wafer using the aspect-ratio-trapping technique were reported. But, the performance of the Ge pFET was limited by the fact that the trap-assisted tunneling and a band-to-band tunneling leakage mechanism is responsible for an elevated bulk current limiting the OFF-state drain current.
Journal ArticleDOI
High-hole mobility polycrystalline Ge on an insulator formed by controlling precursor atomic density for solid-phase crystallization.
TL;DR: This study investigates the low-temperature solid-phase crystallization (SPC) of Ge on a glass substrate, focusing on the precursor conditions, to form SPC-Ge with a hole mobility of 340 cm2/Vs, the highest value among semiconductor thin films grown on insulators at low temperature (<900 °C).
Journal ArticleDOI
Recent advances in germanium nanocrystals: Synthesis, optical properties and applications
TL;DR: Germanium nanocrystals (Ge NCs) have recently attracted renewed scientific interest as environmentally friendlier alternatives to classical II-VI and IV-VI QDs containing toxic elements such as Hg, Cd and Pb.
References
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Proceedings ArticleDOI
A 45nm Logic Technology with High-k+Metal Gate Transistors, Strained Silicon, 9 Cu Interconnect Layers, 193nm Dry Patterning, and 100% Pb-free Packaging
Kaizad Mistry,C. Allen,C. Auth,B. Beattie,Daniel B. Bergstrom,M. Bost,M. Brazier,M. Buehler,Annalisa Cappellani,R. Chau,C. H. Choi,G. Ding,K. Fischer,Tahir Ghani,R. Grover,W. Han,D. Hanken,M. Hattendorf,J. He,J. Hicks,R. Huessner,D. Ingerly,Pulkit Jain,R. James,L. Jong,Subhash M. Joshi,C. Kenyon,K. Kuhn,K. Lee,Huichu Liu,J. Maiz,B. Mclntyre,P. Moon,J. Neirynck,S. Pae,C. Parker,D. Parsons,Chetan Prasad,L. Pipes,M. Prince,Pushkar Ranade,T. Reynolds,J. Sandford,Lucian Shifren,J. Sebastian,J. Seiple,D. Simon,Swaminathan Sivakumar,Pete Smith,C. Thomas,T. Troeger,P. Vandervoorn,S. Williams,K. Zawadzki +53 more
TL;DR: In this paper, a 45 nm logic technology is described that for the first time incorporates high-k + metal gate transistors in a high volume manufacturing process, resulting in the highest drive currents yet reported for NMOS and PMOS.
Proceedings ArticleDOI
A 90nm high volume manufacturing logic technology featuring novel 45nm gate length strained silicon CMOS transistors
Tahir Ghani,Mark Armstrong,C. Auth,M. Bost,P. Charvat,G. Glass,T. Hoffmann,K. Johnson,C. Kenyon,Jason Klaus,B. McIntyre,Kaizad Mistry,Anand Portland Murthy,J. Sandford,M. Silberstein,Swaminathan Sivakumar,Pete Smith,K. Zawadzki,Scott E. Thompson,M. Bohr +19 more
TL;DR: In this article, the authors describe a novel strained transistor architecture which is incorporated into a 90nm logic technology on 300mm wafers, which features an epitaxially grown strained SiGe film embedded in the source drain regions.
Journal ArticleDOI
Controlling threading dislocation densities in Ge on Si using graded SiGe layers and chemical-mechanical polishing
TL;DR: In this paper, a method of controlling threading dislocation densities in Ge on Si involving graded SiGe layers and chemical-mechanical polishing (CMP) is presented.
Journal ArticleDOI
High-k/Ge MOSFETs for future nanoelectronics
TL;DR: In this article, the opportunities and challenges of high-k/Ge MOSFETs are discussed on the basis of the material properties of Ge oxide to provide insights for future progress.
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