Academic and industry research progress in germanium nanodevices
TL;DR: Germanium-based transistors have the potential to operate at high speeds with low power requirements and might therefore be used in non-silicon-based semiconductor technology in the future.
Abstract: Silicon has enabled the rise of the semiconductor electronics industry, but it was not the first material used in such devices. During the 1950s, just after the birth of the transistor, solid-state devices were almost exclusively manufactured from germanium. Today, one of the key ways to improve transistor performance is to increase charge-carrier mobility within the device channel. Motivated by this, the solid-state device research community is returning to investigating the high-mobility material germanium. Germanium-based transistors have the potential to operate at high speeds with low power requirements and might therefore be used in non-silicon-based semiconductor technology in the future.
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01 Jan 2015TL;DR: In this paper, the growth of semiconductor nanocrystals, including quantum well, wire, nanowire, and quantum dot with selective area growth, is summarized and the position-controlled growth of nanocrystal by using faceting growth and mechanisms is described.
Abstract: This chapter summarizes the growth of semiconductor nanocrystals, including quantum well, wire, nanowire, and quantum dot with selective-area growth. The position-controlled growth of nanocrystals by using faceting growth and mechanisms is described. In addition, microchannel epitaxy is outlined as one of the types of selective-area epitaxy.
4 citations
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TL;DR: In this article, the effects of carbon atoms on solid-phase epitaxial growth of Ge on Si(100) have been studied and the surface morphology after annealing changed depending on deposited amounts of C and deposition temperature of Ge.
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TL;DR: In this article , the germanium nanomembrane-based bioresorbable electronic sensors were demonstrated to successfully distinguish the crosstalk of different physiological signals, such as temperature and strain, suggesting the significant prospect for the construction of dual or multi-parameter biosensors.
Abstract: Abstract Transient electronics that can disappear or degrade via physical disintegration or chemical reaction over a pre-defined operational period provide essential for their applications in implantable bioelectronics due to the complete elimination of the second surgical extraction. However, the dissolution of commonly utilized bioresorbable materials often accompanies hydrogen production, which may cause potential or irreparable harm to the human body. This paper introduces germanium nanomembrane-based bioresorbable electronic sensors, where the chemical dissolution of all utilized materials in biofluidic theoretically have no gaseous products. In particular, the superior electronic transport of germanium enables the demonstrated bioresorbable electronic sensors to successfully distinguish the crosstalk of different physiological signals, such as temperature and strain, suggesting the significant prospect for the construction of dual or multi-parameter biosensors. Systematical studies reveal the gauge factor and temperature coefficient of resistance comparable to otherwise similar devices with gaseous products during their dissolution.
4 citations
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TL;DR: In this paper, the role of hole diameter on plasma density in radio frequency hollow cathode discharge (HCD) was investigated in experiments and in simulation based on two-dimensional (2D) fluid model.
Abstract: In this paper, the electron density in radio frequency (RF) hollow cathode discharge (HCD) is investigated in experiments and in simulation based on two-dimensional (2D) fluid model. The role of hole diameter on plasma density in RF HCD have been explored at various gas pressures. It is found that the optimal hole size for maximum plasma density decreases along with the increase of gas pressure, which is confirmed by simulated results. The simulations reveal that the high plasma density is owing to the hollow cathode effect in the hollow cathode. It is obtained that the optimal hole diameter in RF HCD is approximately sum of twice thickness of plasma sheath and triple the electron-neutral mean free path.
4 citations
References
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01 Dec 2007TL;DR: In this paper, a 45 nm logic technology is described that for the first time incorporates high-k + metal gate transistors in a high volume manufacturing process, resulting in the highest drive currents yet reported for NMOS and PMOS.
Abstract: A 45 nm logic technology is described that for the first time incorporates high-k + metal gate transistors in a high volume manufacturing process. The transistors feature 1.0 nm EOT high-k gate dielectric, dual band edge workfunction metal gates and third generation strained silicon, resulting in the highest drive currents yet reported for NMOS and PMOS. The technology also features trench contact based local routing, 9 layers of copper interconnect with low-k ILD, low cost 193 nm dry patterning, and 100% Pb-free packaging. Process yield, performance and reliability are demonstrated on 153 Mb SRAM arrays with SRAM cell size of 0.346 mum2, and on multiple microprocessors.
973 citations
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08 Dec 2003TL;DR: In this article, the authors describe a novel strained transistor architecture which is incorporated into a 90nm logic technology on 300mm wafers, which features an epitaxially grown strained SiGe film embedded in the source drain regions.
Abstract: This paper describes the details of a novel strained transistor architecture which is incorporated into a 90nm logic technology on 300mm wafers The unique strained PMOS transistor structure features an epitaxially grown strained SiGe film embedded in the source drain regions Dramatic performance enhancement relative to unstrained devices are reported These transistors have gate length of 45nm and 50nm for NMOS and PMOS respectively, 12nm physical gate oxide and Ni salicide World record PMOS drive currents of 700/spl mu/A//spl mu/m (high V/sub T/) and 800/spl mu/A//spl mu/m (low V/sub T/) at 12V are demonstrated NMOS devices exercise a highly tensile silicon nitride capping layer to induce tensile strain in the NMOS channel region High NMOS drive currents of 126mA//spl mu/m (high VT) and 145mA//spl mu/m (low VT) at 12V are reported The technology is mature and is being ramped into high volume manufacturing to fabricate next generation Pentium/spl reg/ and Intel/spl reg/ Centrino/spl trade/ processor families
729 citations
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TL;DR: In this paper, a method of controlling threading dislocation densities in Ge on Si involving graded SiGe layers and chemical-mechanical polishing (CMP) is presented.
Abstract: A method of controlling threading dislocation densities in Ge on Si involving graded SiGe layers and chemical-mechanical polishing (CMP) is presented. This method has allowed us to grow a relaxed graded buffer to 100% Ge without the increase in threading dislocation density normally observed in thick graded structures. This sample has been characterized by transmission electron microscopy, etch-pit density, atomic force microscopy, Nomarski optical microscopy, and triple-axis x-ray diffraction. Compared to other relaxed graded buffers in which CMP was not implemented, this sample exhibits improvements in threading dislocation density and surface roughness. We have also made process modifications in order to eliminate particles due to gas-phase nucleation and cracks due to thermal mismatch strain. We have achieved relaxed Ge on Si with a threading dislocation density of 2.1×106 cm−2, and we expect that further process refinements will lead to lower threading dislocation densities on the order of bulk Ge su...
620 citations
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TL;DR: In this article, the opportunities and challenges of high-k/Ge MOSFETs are discussed on the basis of the material properties of Ge oxide to provide insights for future progress.
443 citations