Academic and industry research progress in germanium nanodevices
TL;DR: Germanium-based transistors have the potential to operate at high speeds with low power requirements and might therefore be used in non-silicon-based semiconductor technology in the future.
Abstract: Silicon has enabled the rise of the semiconductor electronics industry, but it was not the first material used in such devices. During the 1950s, just after the birth of the transistor, solid-state devices were almost exclusively manufactured from germanium. Today, one of the key ways to improve transistor performance is to increase charge-carrier mobility within the device channel. Motivated by this, the solid-state device research community is returning to investigating the high-mobility material germanium. Germanium-based transistors have the potential to operate at high speeds with low power requirements and might therefore be used in non-silicon-based semiconductor technology in the future.
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01 Jan 2012
TL;DR: In this paper, an unexpected structure organization was found through molecular dynamics simulations of substoichiometric GeO and GeO2 interfaces, where a majority of germanium and oxygen atoms are threefold coordinated, forming valence alternation pairs (VAPs).
Abstract: The performance of silicon based microelectronic circuits reaches the end of the roadmap. New material systems are required for further improvements in speed and power consumption. Germanium is a possible candidate to substitute silicon for microelectronic devices. Its hole mobility is the highest of all semiconductor materials. Together with its lower band gap it could be an ideal material for energy-saving devices. This thesis is dedicated to first principles studies of the Ge/GeO2 interface through hybrid density functional theory. The substoichiometric region of the interface is of special interest. A wide substoichiometric region is supported by total energy calculations of a set of crystalline model systems. An unexpected structure organization was found through molecular dynamics simulations of substoichiometric GeO. We found that a majority of germanium and oxygen atoms are threefold coordinated, forming valence alternation pairs (VAPs). A detailed energetic analysis located the VAPs in the low-oxygen region of the interface. VAPs show interesting properties : They are prone to charge trapping. The electron trapping level might explain the bad performance of n-type doped devices. Furthermore, VAPs might be at the origin of the difficulties of H passivation at the Ge/GeO2 interface. Since threefold Ge atoms are negatively charged and threefold O atoms are positively charged, VAPs give rise to dipoles. These dipoles may reduce the interface dipole created by the electronegativity difference in the Ge-3O bond. With this mechanism, we can explain the wide range of experimental valence band offsets (VBOs) with the occurrence of different density levels of VAPs at the Ge/GeO2 interface. This suggestion is further confirmed by the determination of the VBO and Ge 3d core-level shift for an atomistic model structure of the Ge/GeO2 interface. Both values are systematically lower than typical experimental values for the Ge/GeO2 interface. Taking the extra dipole into account, our calculated VBOs and XPS shifts are in excellent agreement with experimental values. These results confirm that the structural properties of the Ge/GeO2 interface deviate significantly from its Si counterpart.
3 citations
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TL;DR: A pentagonal hetero-prismatic structural motif was found for singly transition metal doped M@Ge5E5+ clusters, where the transition metal atom is located at the centre of a (5/5) Ge5E 5 prism in which Ge is mixed with either P or As atoms as mentioned in this paper.
Abstract: A pentagonal hetero-prismatic structural motif was found for singly transition metal doped M@Ge5E5+ clusters, where the transition metal atom is located at the centre of a (5/5) Ge5E5 prism in which Ge is mixed with either P or As atoms. Structural characterization indicates that each (5/5) Ge5E5 prism is established by joining of two Ge3E2 and Ge2E3 strings in a prismatic fashion rather than two Ge5 and E5 strings. Each string results from a remarkable mixture of Ge and E atoms and contains only one E–E connection due to the fact that Ge–E bonds are much stronger than E–E connections. From the donor–acceptor perspective, the Ge5E5 tube donates electrons to the M center, which behaves as an acceptor. NBO atomic charge and ELI_D analyses demonstrate such electrostatic interactions of the M dopant with a Ge5E5+ tube which likely induce thermodynamic stability for the resulting M@Ge5E5+ cluster. CMO analysis illustrates that the conventional 18 electron count is recovered in the M@Ge5E5+ cations.
3 citations
TL;DR: In this paper, the electrostatic performance of p-type nanowires (NWs) made of InSb and GaSb, with special focus on their gate capacitance behavior, is analyzed and compared to that achieved by traditional semiconductors usually employed for p-MOS such as Si and Ge.
Abstract: The electrostatic performance of p-type nanowires (NWs) made of InSb and GaSb, with special focus on their gate capacitance behavior, is analyzed and compared to that achieved by traditional semiconductors usually employed for p-MOS such as Si and Ge. To do so, a self-consistent kp simulator has been implemented to achieve an accurate description of the Valence Band and evaluate the charge behavior as a function of the applied gate bias. The contribution and role of the constituent capacitances, namely the insulator, centroid and quantum ones are assessed. It is demonstrated that the centroid and quantum capacitances are strongly dependent on the semiconductor material. We find a good inherent electrostatic performance of GaSb and InSb NWs, comparable to their Ge and Si counterparts making these III-Sb compounds good candidates for future technological nodes.
3 citations
TL;DR: In this article, the presence of the GeO 2 IL changes the effective work function (eWF) of the gate stack when annealed after high-k dielectric deposition.
Abstract: The use of a GeO 2 interfacial layer (IL) between a high-k dielectric and a Ge substrate helps to reduce the interface state density in Ge MOS devices. We report that the presence of the GeO 2 IL changes the effective work function (eWF) of the gate stack when annealed after high-k dielectric deposition. The eWF is reduced from 4.31 eV to 3.98 eV for TaN and from 5.00 eV to 4.44 eV for Ni. Consequently, the threshold voltage ( V th ) decreases from 0.69 V to 0.21 V for Ni after post deposition annealing. Our investigation confirms that the generation of oxygen vacancies in the GeO 2 IL near the Ge substrate is the main cause of the eWF modulation. In addition, the reliability of the GeO 2 IL is investigated via the conductance method and a constant-current stress test.
3 citations
01 Jan 2021
TL;DR: A review of the most relevant experimental results demonstrating the ability of nanosecond laser annealing to achieve dopant activation well above the solid solubility limit is presented in this paper.
Abstract: This chapter presents a review of the most relevant experimental results demonstrating the ability of nanosecond laser annealing to achieve dopant activation well above the solid solubility limit. Several distinctive materials science issues related to laser kinetics in the melt regime are reviewed, including melt temperature differences between amorphous and crystalline phases, melt front propagation, melt duration, recrystallization velocity, and solute trapping. Finally, the morphology, crystalline nature, and residual damage of Si, Ge, and SiGe materials submitted to nanosecond laser anneals in the melt regime are discussed according to the material fabrication history as well as the laser anneal conditions. Due to the richness and relevance of numerous seminal works published in the late 1970s–the early 1980s in this domain, the results reported in this chapter are mainly presented in the form of a historical review and perspective. In particular, the concepts of above-equilibrium solubility and thermal stability are first discussed in general for Si and Ge, while for both materials, the main results are structured in terms of Group III elements (p-type dopants) and Group V elements (n-type dopants). Group VI elements for n-type doping of Si are also considered.
3 citations
References
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01 Dec 2007
TL;DR: In this paper, a 45 nm logic technology is described that for the first time incorporates high-k + metal gate transistors in a high volume manufacturing process, resulting in the highest drive currents yet reported for NMOS and PMOS.
Abstract: A 45 nm logic technology is described that for the first time incorporates high-k + metal gate transistors in a high volume manufacturing process. The transistors feature 1.0 nm EOT high-k gate dielectric, dual band edge workfunction metal gates and third generation strained silicon, resulting in the highest drive currents yet reported for NMOS and PMOS. The technology also features trench contact based local routing, 9 layers of copper interconnect with low-k ILD, low cost 193 nm dry patterning, and 100% Pb-free packaging. Process yield, performance and reliability are demonstrated on 153 Mb SRAM arrays with SRAM cell size of 0.346 mum2, and on multiple microprocessors.
973 citations
08 Dec 2003
TL;DR: In this article, the authors describe a novel strained transistor architecture which is incorporated into a 90nm logic technology on 300mm wafers, which features an epitaxially grown strained SiGe film embedded in the source drain regions.
Abstract: This paper describes the details of a novel strained transistor architecture which is incorporated into a 90nm logic technology on 300mm wafers The unique strained PMOS transistor structure features an epitaxially grown strained SiGe film embedded in the source drain regions Dramatic performance enhancement relative to unstrained devices are reported These transistors have gate length of 45nm and 50nm for NMOS and PMOS respectively, 12nm physical gate oxide and Ni salicide World record PMOS drive currents of 700/spl mu/A//spl mu/m (high V/sub T/) and 800/spl mu/A//spl mu/m (low V/sub T/) at 12V are demonstrated NMOS devices exercise a highly tensile silicon nitride capping layer to induce tensile strain in the NMOS channel region High NMOS drive currents of 126mA//spl mu/m (high VT) and 145mA//spl mu/m (low VT) at 12V are reported The technology is mature and is being ramped into high volume manufacturing to fabricate next generation Pentium/spl reg/ and Intel/spl reg/ Centrino/spl trade/ processor families
729 citations
TL;DR: In this paper, a method of controlling threading dislocation densities in Ge on Si involving graded SiGe layers and chemical-mechanical polishing (CMP) is presented.
Abstract: A method of controlling threading dislocation densities in Ge on Si involving graded SiGe layers and chemical-mechanical polishing (CMP) is presented. This method has allowed us to grow a relaxed graded buffer to 100% Ge without the increase in threading dislocation density normally observed in thick graded structures. This sample has been characterized by transmission electron microscopy, etch-pit density, atomic force microscopy, Nomarski optical microscopy, and triple-axis x-ray diffraction. Compared to other relaxed graded buffers in which CMP was not implemented, this sample exhibits improvements in threading dislocation density and surface roughness. We have also made process modifications in order to eliminate particles due to gas-phase nucleation and cracks due to thermal mismatch strain. We have achieved relaxed Ge on Si with a threading dislocation density of 2.1×106 cm−2, and we expect that further process refinements will lead to lower threading dislocation densities on the order of bulk Ge su...
620 citations
TL;DR: In this article, the opportunities and challenges of high-k/Ge MOSFETs are discussed on the basis of the material properties of Ge oxide to provide insights for future progress.
443 citations