Academic and industry research progress in germanium nanodevices
TL;DR: Germanium-based transistors have the potential to operate at high speeds with low power requirements and might therefore be used in non-silicon-based semiconductor technology in the future.
Abstract: Silicon has enabled the rise of the semiconductor electronics industry, but it was not the first material used in such devices. During the 1950s, just after the birth of the transistor, solid-state devices were almost exclusively manufactured from germanium. Today, one of the key ways to improve transistor performance is to increase charge-carrier mobility within the device channel. Motivated by this, the solid-state device research community is returning to investigating the high-mobility material germanium. Germanium-based transistors have the potential to operate at high speeds with low power requirements and might therefore be used in non-silicon-based semiconductor technology in the future.
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TL;DR: The formation of pseudointrinsic InAs segment is found to be important to make a normally off transistor with a steep subthreshold slope.
Abstract: We report changes of turn-on voltage in InAs-Si heterojunction steep subthreshold-slope transistors by the Zn-pulsed doping technique for InAs nanowire channels. The doping of the nanowire channel moderately changes turn-on voltage from negative to positive voltage, while keeping a steep subthreshold-slope of 30 mV/decade under reverse bias direction. The formation of pseudointrinsic InAs segment is found to be important to make a normally off transistor with a steep subthreshold slope.
64 citations
TL;DR: In this paper, the structural, electronic and magnetic properties of VGen-/0 (n = 3-12) clusters were investigated using anion photoelectron spectroscopy in combination with density functional theory calculations.
Abstract: The structural, electronic and magnetic properties of VGen-/0 (n = 3-12) clusters were investigated using anion photoelectron spectroscopy in combination with density functional theory calculations. We found that the dominant geometries are exohedral for the VGen-/0 clusters with n <= 7. The VGe8-/0 clusters have half-encapsulated boat-shaped structures, and the opening of the boat-shaped structure is gradually covered by the additional Ge atoms to form Ge-n cage from n = 9-11. At n = 12, a D-3d distorted hexagonal prism cage structure is formed. According to the natural population analysis, for both anionic and neutral VGen clusters of n = 8-12, there is electron transfer from the Ge framework to the V atom and the total magnetic moments decrease to the minima. The electron transfer pattern and the minimization of the magnetic moments for these clusters are related to their structural evolution.
64 citations
TL;DR: In this article, the Si-doped HfO2 thin films have favorably improved ferroelectric properties on the p+Ge substrate due to the lack of a dielectric interfacial layer between HmO2 and Ge.
Abstract: Ferroelectric Si-doped HfO2 thin films are integrated into three different device stacks with a p+ Ge substrate, a p+ Si substrate, and a TaN bottom metal gate. The ferroelectric behavior of the Si-doped HfO2 thin films is strongly dependent on the bottom interfaces. The Si-doped HfO2 thin films have favorably improved ferroelectric properties on the p+ Ge substrate due to the lack of a dielectric interfacial layer between HfO2 and Ge. The low-voltage operation and cycling stability of Si-doped HfO2 ferroelectric thin films on Ge can lead to the realization of high performance, robust Ge ferroelectric field-effect transistors for nonvolatile memory applications.
61 citations
Cites methods from "Academic and industry research prog..."
...One alternative is to use a different semiconductor material as the template for the ferroelectric field effect transistor such as Ge which is a candidate for future p-type FETs due to its high hole mobility [7]....
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TL;DR: In this article, phase pure Ge1-x-snx nanoalloys with sizes in the range of 15-23 and 3.4-4.6 nm and Sn compositions from x = 0.000-0.279 were reported.
Abstract: Ge1–xSnx alloys are among a small class of benign semiconductors with composition tunable bandgaps in the near-infrared (NIR) spectrum. As the amount of Sn is increased, the band energy decreases and a transition from indirect to direct band structure occurs. Hence, they are prime candidates for fabrication of Si-compatible electronic and photonic devices, field effect transistors, and novel charge storage device applications. Success has been achieved with the growth of Ge1–xSnx thin film alloys with Sn compositions up to 34%. However, the synthesis of nanocrystalline alloys has proven difficult, because of larger discrepancies (∼14%) in lattice constants. Moreover, little is known about the chemical factors that govern the growth of Ge1–xSnx nanoalloys and the effects of quantum confinement on structure and optical properties. Herein, we report the synthesis of phase pure Ge1–xSnx nanoalloys with sizes in the range of 15–23 and 3.4–4.6 nm and Sn compositions from x = 0.000–0.279, including the factors t...
61 citations
TL;DR: The transfer of electrons from the Gen framework to the Co atom and the minimization of the magnetic moments are related to the evolution of CoGe(n) structures from exo- to endohedral.
Abstract: A series of cobalt-doped germanium clusters, CoGe(n)(-/0) (n=2-11), are investigated by using anion photoelectron spectroscopy combined with density functional theory calculations. For both anionic and neutral CoGe(n) (n=2-11) clusters, the critical size of the transition from exo- to endohedral structures is n=9. Natural population analysis shows that there is electron transfer from the Ge(n) framework to the Co atom at n=7-11 for both anionic and neutral CoGe(n) clusters. The magnetic moments of the anionic and neutral CoGe(n) clusters decrease to the lowest values at n=10 and 11. The transfer of electrons from the Gen framework to the Co atom and the minimization of the magnetic moments are related to the evolution of CoGe(n) structures from exo- to endohedral.
58 citations
References
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01 Dec 2007
TL;DR: In this paper, a 45 nm logic technology is described that for the first time incorporates high-k + metal gate transistors in a high volume manufacturing process, resulting in the highest drive currents yet reported for NMOS and PMOS.
Abstract: A 45 nm logic technology is described that for the first time incorporates high-k + metal gate transistors in a high volume manufacturing process. The transistors feature 1.0 nm EOT high-k gate dielectric, dual band edge workfunction metal gates and third generation strained silicon, resulting in the highest drive currents yet reported for NMOS and PMOS. The technology also features trench contact based local routing, 9 layers of copper interconnect with low-k ILD, low cost 193 nm dry patterning, and 100% Pb-free packaging. Process yield, performance and reliability are demonstrated on 153 Mb SRAM arrays with SRAM cell size of 0.346 mum2, and on multiple microprocessors.
973 citations
08 Dec 2003
TL;DR: In this article, the authors describe a novel strained transistor architecture which is incorporated into a 90nm logic technology on 300mm wafers, which features an epitaxially grown strained SiGe film embedded in the source drain regions.
Abstract: This paper describes the details of a novel strained transistor architecture which is incorporated into a 90nm logic technology on 300mm wafers The unique strained PMOS transistor structure features an epitaxially grown strained SiGe film embedded in the source drain regions Dramatic performance enhancement relative to unstrained devices are reported These transistors have gate length of 45nm and 50nm for NMOS and PMOS respectively, 12nm physical gate oxide and Ni salicide World record PMOS drive currents of 700/spl mu/A//spl mu/m (high V/sub T/) and 800/spl mu/A//spl mu/m (low V/sub T/) at 12V are demonstrated NMOS devices exercise a highly tensile silicon nitride capping layer to induce tensile strain in the NMOS channel region High NMOS drive currents of 126mA//spl mu/m (high VT) and 145mA//spl mu/m (low VT) at 12V are reported The technology is mature and is being ramped into high volume manufacturing to fabricate next generation Pentium/spl reg/ and Intel/spl reg/ Centrino/spl trade/ processor families
729 citations
TL;DR: In this paper, a method of controlling threading dislocation densities in Ge on Si involving graded SiGe layers and chemical-mechanical polishing (CMP) is presented.
Abstract: A method of controlling threading dislocation densities in Ge on Si involving graded SiGe layers and chemical-mechanical polishing (CMP) is presented. This method has allowed us to grow a relaxed graded buffer to 100% Ge without the increase in threading dislocation density normally observed in thick graded structures. This sample has been characterized by transmission electron microscopy, etch-pit density, atomic force microscopy, Nomarski optical microscopy, and triple-axis x-ray diffraction. Compared to other relaxed graded buffers in which CMP was not implemented, this sample exhibits improvements in threading dislocation density and surface roughness. We have also made process modifications in order to eliminate particles due to gas-phase nucleation and cracks due to thermal mismatch strain. We have achieved relaxed Ge on Si with a threading dislocation density of 2.1×106 cm−2, and we expect that further process refinements will lead to lower threading dislocation densities on the order of bulk Ge su...
620 citations
TL;DR: In this article, the opportunities and challenges of high-k/Ge MOSFETs are discussed on the basis of the material properties of Ge oxide to provide insights for future progress.
443 citations