Academic and industry research progress in germanium nanodevices
TL;DR: Germanium-based transistors have the potential to operate at high speeds with low power requirements and might therefore be used in non-silicon-based semiconductor technology in the future.
Abstract: Silicon has enabled the rise of the semiconductor electronics industry, but it was not the first material used in such devices. During the 1950s, just after the birth of the transistor, solid-state devices were almost exclusively manufactured from germanium. Today, one of the key ways to improve transistor performance is to increase charge-carrier mobility within the device channel. Motivated by this, the solid-state device research community is returning to investigating the high-mobility material germanium. Germanium-based transistors have the potential to operate at high speeds with low power requirements and might therefore be used in non-silicon-based semiconductor technology in the future.
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Dissertation•
08 Mar 2018
TL;DR: In this article, the authors present a set of films SGOI-On-Insulator (SGOI: SiGe-OnInsulator) with high concentration in Ge and low concentration in SiGe on insulators.
Abstract: La reduction continue des dimensions des transistors depuis les annees 60 est a l’origine de l’explosion des usages de l’electronique. Toutefois, la reduction des dimensions a l’echelle nanometrique s’accompagne de nouvelles difficultes qui tendent a limiter les gains des transistors en termes de performances et de consommation.Afin de surmonter ces obstacles et maintenir cette dynamique, des canaux a base de nouveaux materiaux a forte mobilite et de nouvelles architectures de transistors sont desormais utilisees ou a l’etude. L’interet de films SiGe contraint en compression sur isolant (SGOI: SiGe-On-Insulator) ultra-minces est double : ils beneficient de la forte mobilite des trous du SiGe contraint en compression ainsi que du meilleur controle electrostatique des structures dites « sur isolant ». Des films SGOI presentant une forte concentration en Ge et une importante contrainte peuvent etre fabriques par une technique industrielle appelee condensation. Cette technique repose sur deux processus simultanes : l’oxydation thermique et selective du SiGe (seul le Si est oxyde) et l’inter-diffusion du SiGe entre l’oxyde thermique et l’oxyde enterre qui se comporte comme une barriere a la diffusion.L’utilisation de cette technique dans un environnement industriel necessite de relever deux defis : maitriser les mecanismes et la cinetique d’oxydation, et atteindre les plus fortes contraintes et qualites cristallines pour lesfilms SGOI.La cinetique de plusieurs procedes d’oxydation industriels et pertinents au regard des besoins technologiques actuels est etudiee a l’aide d’une nouvelle methodologie d’analyse quantitative. Nous etablissons une correlationentre le coefficient de diffusion de l’espece oxydante, qui determine la cinetique d’oxydation, la concentration en Ge a l’interface d’oxydation, et la densite de l’oxyde mesuree par reflectivite de rayons X sur une ligne desynchrotron.Puis, nous avons fabrique des films SGOI presentant des concentrations en Ge jusqu’a 80%. Nous discutons l’evolution de la contrainte de ces films en fonction des parametres du procede et des niveaux de contrainte. Enfin,nous mettons en evidence les effets du procede de condensation sur la qualite cristalline du film SiGe aux interfaces avec les oxydes grâce a l’effet de canalisation d’une technique de retrodiffusion d’ions a moyenne energie (MEIS : Medium Energy Ion Scattering)
3 citations
TL;DR: The coupled Ge NP-Er emission shows a negligible thermal quenching from 10 K to room temperature that is related to Er3+ de-excitation through thermally activated defect states.
Abstract: The potential of Ge nanoparticles (NPs) embedded in Al2O3 with tunable effective optical bandgap values in the range of 1.0–3.3 eV to induce enhanced Er3+ light emission is investigated. We demonstrate nonresonant indirect excitation of the Er3+ ions mediated by the Ge NPs at room temperature. Efficient Er3+ light emission enhancement is obtained for Ge NPs with large effective optical bandgaps in the range of 1.85 to 2.8 eV. The coupled Ge NP–Er emission shows a negligible thermal quenching from 10 K to room temperature that is related to Er3+ de-excitation through thermally activated defect states.
3 citations
TL;DR: In this article, the scaling properties of germanium-silicon-germanium (Ge-Si1-xGex) core-shell nanowire (NW) n-type, Ω-gate field effect transistors (FETs) were investigated.
Abstract: We present the realization and scaling properties of germanium-silicon-germanium (Ge-Si1-xGex) core-shell nanowire (NW) n-type, Ω-gate field-effect transistors (FETs). The devices show superior performance to the counterparts without the Si1-xGex shell. With a channel length (Lch) of 380 nm and a diameter of 40 nm, we demonstrate a subthreshold swing of 180 mV/dec, and an ON-current (ION) of 60 μA/μm, comparable with recent results in Ge n-type FinFETs fabricated by top-down techniques. By systematically studying the scaling properties, we identify the contribution of the channel and contact resistances to device characteristics. We conclude that ION is not limited by the contact resistance but rather by a relatively large channel resistance, presumably associated with a high-interface trap density (Dit).
3 citations
Cites background from "Academic and industry research prog..."
...Devices utilizing germanium or silicon– germanium compounds as active regions are of particular interest, thanks to their compatibility with current Si-based technology and high electron and hole mobility [1]–[5]....
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TL;DR: In this paper, the evolution of structural and electronic properties, and dynamical fluxionality of B2Gen−/0 (n = 3-12) clusters were investigated using DFT calculations combined with CALYPSO global searching algo.
Abstract: The evolution of structural and electronic properties, and dynamical fluxionality of B2Gen−/0 (n = 3–12) clusters are investigated using DFT calculations combined with CALYPSO global searching algo...
3 citations
References
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01 Dec 2007
TL;DR: In this paper, a 45 nm logic technology is described that for the first time incorporates high-k + metal gate transistors in a high volume manufacturing process, resulting in the highest drive currents yet reported for NMOS and PMOS.
Abstract: A 45 nm logic technology is described that for the first time incorporates high-k + metal gate transistors in a high volume manufacturing process. The transistors feature 1.0 nm EOT high-k gate dielectric, dual band edge workfunction metal gates and third generation strained silicon, resulting in the highest drive currents yet reported for NMOS and PMOS. The technology also features trench contact based local routing, 9 layers of copper interconnect with low-k ILD, low cost 193 nm dry patterning, and 100% Pb-free packaging. Process yield, performance and reliability are demonstrated on 153 Mb SRAM arrays with SRAM cell size of 0.346 mum2, and on multiple microprocessors.
973 citations
08 Dec 2003
TL;DR: In this article, the authors describe a novel strained transistor architecture which is incorporated into a 90nm logic technology on 300mm wafers, which features an epitaxially grown strained SiGe film embedded in the source drain regions.
Abstract: This paper describes the details of a novel strained transistor architecture which is incorporated into a 90nm logic technology on 300mm wafers The unique strained PMOS transistor structure features an epitaxially grown strained SiGe film embedded in the source drain regions Dramatic performance enhancement relative to unstrained devices are reported These transistors have gate length of 45nm and 50nm for NMOS and PMOS respectively, 12nm physical gate oxide and Ni salicide World record PMOS drive currents of 700/spl mu/A//spl mu/m (high V/sub T/) and 800/spl mu/A//spl mu/m (low V/sub T/) at 12V are demonstrated NMOS devices exercise a highly tensile silicon nitride capping layer to induce tensile strain in the NMOS channel region High NMOS drive currents of 126mA//spl mu/m (high VT) and 145mA//spl mu/m (low VT) at 12V are reported The technology is mature and is being ramped into high volume manufacturing to fabricate next generation Pentium/spl reg/ and Intel/spl reg/ Centrino/spl trade/ processor families
729 citations
TL;DR: In this paper, a method of controlling threading dislocation densities in Ge on Si involving graded SiGe layers and chemical-mechanical polishing (CMP) is presented.
Abstract: A method of controlling threading dislocation densities in Ge on Si involving graded SiGe layers and chemical-mechanical polishing (CMP) is presented. This method has allowed us to grow a relaxed graded buffer to 100% Ge without the increase in threading dislocation density normally observed in thick graded structures. This sample has been characterized by transmission electron microscopy, etch-pit density, atomic force microscopy, Nomarski optical microscopy, and triple-axis x-ray diffraction. Compared to other relaxed graded buffers in which CMP was not implemented, this sample exhibits improvements in threading dislocation density and surface roughness. We have also made process modifications in order to eliminate particles due to gas-phase nucleation and cracks due to thermal mismatch strain. We have achieved relaxed Ge on Si with a threading dislocation density of 2.1×106 cm−2, and we expect that further process refinements will lead to lower threading dislocation densities on the order of bulk Ge su...
620 citations
TL;DR: In this article, the opportunities and challenges of high-k/Ge MOSFETs are discussed on the basis of the material properties of Ge oxide to provide insights for future progress.
443 citations