Academic and industry research progress in germanium nanodevices
TL;DR: Germanium-based transistors have the potential to operate at high speeds with low power requirements and might therefore be used in non-silicon-based semiconductor technology in the future.
Abstract: Silicon has enabled the rise of the semiconductor electronics industry, but it was not the first material used in such devices. During the 1950s, just after the birth of the transistor, solid-state devices were almost exclusively manufactured from germanium. Today, one of the key ways to improve transistor performance is to increase charge-carrier mobility within the device channel. Motivated by this, the solid-state device research community is returning to investigating the high-mobility material germanium. Germanium-based transistors have the potential to operate at high speeds with low power requirements and might therefore be used in non-silicon-based semiconductor technology in the future.
Citations
More filters
Dissertation•
01 Jan 2017
3 citations
Cites background from "Academic and industry research prog..."
...1: III-V compound semiconductors mobility and band gap[24]....
[...]
3 citations
TL;DR: In this paper, a simulation of the heating and phase transitions of an amorphous Ge film on a crystalline Ge substrate is carried out, as well as the diffusive redistribution of the impurity (Sb) under pulsed treatments.
Abstract: To produce heavily doped epitaxial layers, amorphous Ge:Sb films with a thickness of 150 and 300 nm are vacuum-deposited on Ge substrates and are exposed to pulsed nanosecond irradiation of high-power laser (λ = 069 μm) or ion (C+ or H+) beams In the course of laser processing, the irradiated region is optically probed with the registration of the reflection of the probe beam R(t) to control the aggregate state of the film As a result of rapid crystallization, polycrystalline or epitaxial Ge:Sb layers of different thicknesses are formed from the melt Computer simulation of the heating and phase transitions of an amorphous Ge film on a crystalline Ge substrate is carried out, as well as the diffusive redistribution of the impurity (Sb) under pulsed treatments We showed that, due to the volumetric release of the energy of ion beams, it is possible to control the distribution of the Sb impurity up to a depth of 15 μm The simulation results are in good agreement with the experiment
3 citations
TL;DR: In this paper, the development of several germanium-based semiconductor inks is detailed, their printing and post-processing using photonic annealing is demonstrated, and their electro-optic performance is characterized.
Abstract: The ability to add functionality to flexible substrates through additive approaches using electronic and optical materials for wearable or conformal applications has become increasingly important in recent years. In this paper, the development of several germanium based semiconductor inks is detailed, their printing and post-processing using photonic annealing is demonstrated, and their electro-optic performance is characterized. A range of inks were developed, namely a pristine germanium nanoparticle ink, a nickel doped germanium nanoparticle ink, and a hybrid silver nanoparticle/germanium nanoparticle ink. Aerosol jet printing was performed on both rigid substrates and a common flexible polyimide substrate (KaptonTM). Photonic sintering was used on all three printed inks to improve their optoelectronic properties and coalesce the individual particles into a continuous film. Optical and structural characterization of the printed films was performed before and after photonic sintering to investigate morphological changes in the film. Finally, the applicability of these inks in flexible optoelectronic applications was demonstrated by measuring the photo-excited conductivity changes as well as the flexibility of the printed films.
3 citations
30 Jun 2016
TL;DR: In this article, two emerging applications of high-k dielectrics were investigated: (i) germanium based MOSFETs and (ii) high frequency high speed rectifiers for optical rectennas.
Abstract: The evolution of integrated circuit technology over the five decades resulted in scaling down the minimum feature size of a transistor from 10 μm to ~14 nm. The high-k dielectrics were identified as potential candidates to replace SiO2 from 2007 due to the large leakage current observed when scaling down SiO2. These materials captured the attention of many researchers and led them to focus on many emerging applications in addition to metal oxide semiconductor field effect transistors (MOSFET). In this thesis, two emerging applications of high-k dielectrics were investigated: (i) germanium based MOSFETs and (ii) high frequency high speed rectifiers for optical rectennas.
3 citations
References
More filters
01 Dec 2007
TL;DR: In this paper, a 45 nm logic technology is described that for the first time incorporates high-k + metal gate transistors in a high volume manufacturing process, resulting in the highest drive currents yet reported for NMOS and PMOS.
Abstract: A 45 nm logic technology is described that for the first time incorporates high-k + metal gate transistors in a high volume manufacturing process. The transistors feature 1.0 nm EOT high-k gate dielectric, dual band edge workfunction metal gates and third generation strained silicon, resulting in the highest drive currents yet reported for NMOS and PMOS. The technology also features trench contact based local routing, 9 layers of copper interconnect with low-k ILD, low cost 193 nm dry patterning, and 100% Pb-free packaging. Process yield, performance and reliability are demonstrated on 153 Mb SRAM arrays with SRAM cell size of 0.346 mum2, and on multiple microprocessors.
973 citations
08 Dec 2003
TL;DR: In this article, the authors describe a novel strained transistor architecture which is incorporated into a 90nm logic technology on 300mm wafers, which features an epitaxially grown strained SiGe film embedded in the source drain regions.
Abstract: This paper describes the details of a novel strained transistor architecture which is incorporated into a 90nm logic technology on 300mm wafers The unique strained PMOS transistor structure features an epitaxially grown strained SiGe film embedded in the source drain regions Dramatic performance enhancement relative to unstrained devices are reported These transistors have gate length of 45nm and 50nm for NMOS and PMOS respectively, 12nm physical gate oxide and Ni salicide World record PMOS drive currents of 700/spl mu/A//spl mu/m (high V/sub T/) and 800/spl mu/A//spl mu/m (low V/sub T/) at 12V are demonstrated NMOS devices exercise a highly tensile silicon nitride capping layer to induce tensile strain in the NMOS channel region High NMOS drive currents of 126mA//spl mu/m (high VT) and 145mA//spl mu/m (low VT) at 12V are reported The technology is mature and is being ramped into high volume manufacturing to fabricate next generation Pentium/spl reg/ and Intel/spl reg/ Centrino/spl trade/ processor families
729 citations
TL;DR: In this paper, a method of controlling threading dislocation densities in Ge on Si involving graded SiGe layers and chemical-mechanical polishing (CMP) is presented.
Abstract: A method of controlling threading dislocation densities in Ge on Si involving graded SiGe layers and chemical-mechanical polishing (CMP) is presented. This method has allowed us to grow a relaxed graded buffer to 100% Ge without the increase in threading dislocation density normally observed in thick graded structures. This sample has been characterized by transmission electron microscopy, etch-pit density, atomic force microscopy, Nomarski optical microscopy, and triple-axis x-ray diffraction. Compared to other relaxed graded buffers in which CMP was not implemented, this sample exhibits improvements in threading dislocation density and surface roughness. We have also made process modifications in order to eliminate particles due to gas-phase nucleation and cracks due to thermal mismatch strain. We have achieved relaxed Ge on Si with a threading dislocation density of 2.1×106 cm−2, and we expect that further process refinements will lead to lower threading dislocation densities on the order of bulk Ge su...
620 citations
TL;DR: In this article, the opportunities and challenges of high-k/Ge MOSFETs are discussed on the basis of the material properties of Ge oxide to provide insights for future progress.
443 citations