Journal ArticleDOI
Academic and industry research progress in germanium nanodevices
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TLDR
Germanium-based transistors have the potential to operate at high speeds with low power requirements and might therefore be used in non-silicon-based semiconductor technology in the future.Abstract:
Silicon has enabled the rise of the semiconductor electronics industry, but it was not the first material used in such devices. During the 1950s, just after the birth of the transistor, solid-state devices were almost exclusively manufactured from germanium. Today, one of the key ways to improve transistor performance is to increase charge-carrier mobility within the device channel. Motivated by this, the solid-state device research community is returning to investigating the high-mobility material germanium. Germanium-based transistors have the potential to operate at high speeds with low power requirements and might therefore be used in non-silicon-based semiconductor technology in the future.read more
Citations
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DissertationDOI
Engineered High-k Oxides
TL;DR: In this article, two emerging applications of high-k dielectrics were investigated: (i) germanium based MOSFETs and (ii) high frequency high speed rectifiers for optical rectennas.
Journal ArticleDOI
Outer Ring-Shaped Radio Frequency Magnetized Plasma Source for Target Utilization in Specific Area
Md. Amzad Hossain,Yasunori Ohtsu +1 more
TL;DR: In this paper, a capacitively coupled radio frequency outer ring-shaped magnetized plasma discharge has been proposed with a concentrically monopole arrangement of magnets to erode the target in a specific area, especially, near the chamber wall.
Journal ArticleDOI
Synthesis of relaxed Ge0.9Sn0.1/Ge by nanosecond pulsed laser melting
E. Di Russo,Francesco Sgarbossa,Pierpaolo Ranieri,Gianluigi Maggioni,S. Ndiaye,Sébastien Duguay,François Vurpillot,Lorenzo Rigutti,Jean-Luc Rouvière,Vittorio Morandi,D. De Salvador,Enrico Napolitani +11 more
TL;DR: In this article , a new approach to the fabrication of fully relaxed Ge1-ySny layers on Ge wafers with Sn concentration y up to 13 at. % was presented.
Journal ArticleDOI
Dislocation scatterings in p-type Si(1-x)Ge(x) under weak electric field.
TL;DR: A criterion for negating scatterings by dislocations in terms of the controllable parameters such as acceptor dopant density, dislocation density, temperature, and Ge density x, etc is suggested.
Dissertation
Variability and reliability analysis of carbon nanotube technology in the presence of manufacturing imperfections
TL;DR: In this paper, the impact of CNT-specific variations on CNFET performance was analyzed from the point of view of variability and reliability and at different levels, device and circuit level.
References
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Proceedings ArticleDOI
A 45nm Logic Technology with High-k+Metal Gate Transistors, Strained Silicon, 9 Cu Interconnect Layers, 193nm Dry Patterning, and 100% Pb-free Packaging
Kaizad Mistry,C. Allen,C. Auth,B. Beattie,Daniel B. Bergstrom,M. Bost,M. Brazier,M. Buehler,Annalisa Cappellani,R. Chau,C. H. Choi,G. Ding,K. Fischer,Tahir Ghani,R. Grover,W. Han,D. Hanken,M. Hattendorf,J. He,J. Hicks,R. Huessner,D. Ingerly,Pulkit Jain,R. James,L. Jong,Subhash M. Joshi,C. Kenyon,K. Kuhn,K. Lee,Huichu Liu,J. Maiz,B. Mclntyre,P. Moon,J. Neirynck,S. Pae,C. Parker,D. Parsons,Chetan Prasad,L. Pipes,M. Prince,Pushkar Ranade,T. Reynolds,J. Sandford,Lucian Shifren,J. Sebastian,J. Seiple,D. Simon,Swaminathan Sivakumar,Pete Smith,C. Thomas,T. Troeger,P. Vandervoorn,S. Williams,K. Zawadzki +53 more
TL;DR: In this paper, a 45 nm logic technology is described that for the first time incorporates high-k + metal gate transistors in a high volume manufacturing process, resulting in the highest drive currents yet reported for NMOS and PMOS.
Proceedings ArticleDOI
A 90nm high volume manufacturing logic technology featuring novel 45nm gate length strained silicon CMOS transistors
Tahir Ghani,Mark Armstrong,C. Auth,M. Bost,P. Charvat,G. Glass,T. Hoffmann,K. Johnson,C. Kenyon,Jason Klaus,B. McIntyre,Kaizad Mistry,Anand Portland Murthy,J. Sandford,M. Silberstein,Swaminathan Sivakumar,Pete Smith,K. Zawadzki,Scott E. Thompson,M. Bohr +19 more
TL;DR: In this article, the authors describe a novel strained transistor architecture which is incorporated into a 90nm logic technology on 300mm wafers, which features an epitaxially grown strained SiGe film embedded in the source drain regions.
Journal ArticleDOI
Controlling threading dislocation densities in Ge on Si using graded SiGe layers and chemical-mechanical polishing
TL;DR: In this paper, a method of controlling threading dislocation densities in Ge on Si involving graded SiGe layers and chemical-mechanical polishing (CMP) is presented.
Journal ArticleDOI
High-k/Ge MOSFETs for future nanoelectronics
TL;DR: In this article, the opportunities and challenges of high-k/Ge MOSFETs are discussed on the basis of the material properties of Ge oxide to provide insights for future progress.
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