Academic and industry research progress in germanium nanodevices
TL;DR: Germanium-based transistors have the potential to operate at high speeds with low power requirements and might therefore be used in non-silicon-based semiconductor technology in the future.
Abstract: Silicon has enabled the rise of the semiconductor electronics industry, but it was not the first material used in such devices. During the 1950s, just after the birth of the transistor, solid-state devices were almost exclusively manufactured from germanium. Today, one of the key ways to improve transistor performance is to increase charge-carrier mobility within the device channel. Motivated by this, the solid-state device research community is returning to investigating the high-mobility material germanium. Germanium-based transistors have the potential to operate at high speeds with low power requirements and might therefore be used in non-silicon-based semiconductor technology in the future.
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30 Oct 2014
TL;DR: In this paper, the formation of N-type Ge shallow junction is investigated by combining carbon co-implantation and microwave annealing (MWA) method, the junction depth of 34 nm measured by secondary ion mass spectroscopy (SIMS) as well as sheet resistance of 467 ohm/sq measured by Hall is achieved.
Abstract: the formation of N-type Ge shallow junction is investigated in this work. By combining carbon co-implantation and microwave annealing (MWA) method, the junction depth of 34 nm measured by secondary ion mass spectroscopy (SIMS) as well as sheet resistance of 467 ohm/sq measured by Hall is achieved. Results show that the opitimal carbon implantation energy is 8 keV in that distributed carbon ions at such an energy can effectively trap vacancies and phosphorous into immobile clusters. The recrystallization of amorphous layer after MWA annealing is also studied by both ellipsometry and transmission electron microscopy (TEM).
2 citations
TL;DR: In this article , the authors show that a newly developed high temperature, ultra low rate oxidation process can produce homogeneous, fully strained, defect-free and perfectly flat Silicon Germanium (Si1-xGex) On Insulator films when x ≤ 0.33.
2 citations
01 Apr 2017
TL;DR: In this paper, the positive bias temperature instability (PBTI) was reported on Ge n-channel metal oxide semiconductor field effect transistors (nFETs) with a stable and ultrathin (5 A) Al 2 O 3 inter layer (IL) using ultrafast (∼μs) characterization techniques.
Abstract: This work for the first time reports positive bias temperature instability (PBTI) on Ge n-channel metal oxide semiconductor field effect transistors (nFETs) with a stable and ultrathin (5 A) Al 2 O 3 inter layer (IL) using ultrafast (∼μs) characterization techniques Since ∼μs delay time is employed, all possible signatures of trap generation and trapping are captured Trap generation behavior is studied using a detrapping technique that is shown to predict (1) threshold voltage degradation (ΔVT) time exponent (n) independent of gate oxide field and (2) trap-generation signature at IL/high-κ interface This is the first report of such a signature in Ge nFETs PBTI is shown to improve with decrease in high-κ thickness, increase in IL thickness and forming gas annealing Deconvolution of uncorrelated IL/high-Λ interface trap and high-κ bulk trap components from ultrafast data using a compact model shows a stable IL/high-κ interface
2 citations
Cites background from "Academic and industry research prog..."
...Among these, Ge holds significant promise due to its higher electron and hole bulk mobilities (μ) [2], feasible integration on Si [3], high source injection velocity [4], and, low resistance contacts [5] to name a few....
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22 May 2016
TL;DR: The impact of imperfection of CNT substrates based on a recently developed CMOS-compatible self-assembly process on the CNFET CMOS circuit functionalities is studied, and a methodology to estimate material and process requirements according to the circuit-level yield target is provided.
Abstract: Carbon nanotube field effect transistor (CNFET) is one of the most promising emerging technologies, which can potentially outperform the conventional silicon technology with higher speed and lower power. However, most emerging technologies, including CNFETs, often face the challenge of lower device yield due to imperfect material processing. This paper studies the impact of imperfection of CNT substrates based on a recently developed CMOS-compatible self-assembly process on the CNFET CMOS circuit functionalities, and provide a methodology to estimate material and process requirements according to the circuit-level yield target.
2 citations
References
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01 Dec 2007
TL;DR: In this paper, a 45 nm logic technology is described that for the first time incorporates high-k + metal gate transistors in a high volume manufacturing process, resulting in the highest drive currents yet reported for NMOS and PMOS.
Abstract: A 45 nm logic technology is described that for the first time incorporates high-k + metal gate transistors in a high volume manufacturing process. The transistors feature 1.0 nm EOT high-k gate dielectric, dual band edge workfunction metal gates and third generation strained silicon, resulting in the highest drive currents yet reported for NMOS and PMOS. The technology also features trench contact based local routing, 9 layers of copper interconnect with low-k ILD, low cost 193 nm dry patterning, and 100% Pb-free packaging. Process yield, performance and reliability are demonstrated on 153 Mb SRAM arrays with SRAM cell size of 0.346 mum2, and on multiple microprocessors.
973 citations
08 Dec 2003
TL;DR: In this article, the authors describe a novel strained transistor architecture which is incorporated into a 90nm logic technology on 300mm wafers, which features an epitaxially grown strained SiGe film embedded in the source drain regions.
Abstract: This paper describes the details of a novel strained transistor architecture which is incorporated into a 90nm logic technology on 300mm wafers The unique strained PMOS transistor structure features an epitaxially grown strained SiGe film embedded in the source drain regions Dramatic performance enhancement relative to unstrained devices are reported These transistors have gate length of 45nm and 50nm for NMOS and PMOS respectively, 12nm physical gate oxide and Ni salicide World record PMOS drive currents of 700/spl mu/A//spl mu/m (high V/sub T/) and 800/spl mu/A//spl mu/m (low V/sub T/) at 12V are demonstrated NMOS devices exercise a highly tensile silicon nitride capping layer to induce tensile strain in the NMOS channel region High NMOS drive currents of 126mA//spl mu/m (high VT) and 145mA//spl mu/m (low VT) at 12V are reported The technology is mature and is being ramped into high volume manufacturing to fabricate next generation Pentium/spl reg/ and Intel/spl reg/ Centrino/spl trade/ processor families
729 citations
TL;DR: In this paper, a method of controlling threading dislocation densities in Ge on Si involving graded SiGe layers and chemical-mechanical polishing (CMP) is presented.
Abstract: A method of controlling threading dislocation densities in Ge on Si involving graded SiGe layers and chemical-mechanical polishing (CMP) is presented. This method has allowed us to grow a relaxed graded buffer to 100% Ge without the increase in threading dislocation density normally observed in thick graded structures. This sample has been characterized by transmission electron microscopy, etch-pit density, atomic force microscopy, Nomarski optical microscopy, and triple-axis x-ray diffraction. Compared to other relaxed graded buffers in which CMP was not implemented, this sample exhibits improvements in threading dislocation density and surface roughness. We have also made process modifications in order to eliminate particles due to gas-phase nucleation and cracks due to thermal mismatch strain. We have achieved relaxed Ge on Si with a threading dislocation density of 2.1×106 cm−2, and we expect that further process refinements will lead to lower threading dislocation densities on the order of bulk Ge su...
620 citations
TL;DR: In this article, the opportunities and challenges of high-k/Ge MOSFETs are discussed on the basis of the material properties of Ge oxide to provide insights for future progress.
443 citations