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Journal ArticleDOI

Academic and industry research progress in germanium nanodevices

Ravi Pillarisetty1
17 Nov 2011-Nature (Nature Publishing Group)-Vol. 479, Iss: 7373, pp 324-328
TL;DR: Germanium-based transistors have the potential to operate at high speeds with low power requirements and might therefore be used in non-silicon-based semiconductor technology in the future.
Abstract: Silicon has enabled the rise of the semiconductor electronics industry, but it was not the first material used in such devices. During the 1950s, just after the birth of the transistor, solid-state devices were almost exclusively manufactured from germanium. Today, one of the key ways to improve transistor performance is to increase charge-carrier mobility within the device channel. Motivated by this, the solid-state device research community is returning to investigating the high-mobility material germanium. Germanium-based transistors have the potential to operate at high speeds with low power requirements and might therefore be used in non-silicon-based semiconductor technology in the future.
Citations
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Journal ArticleDOI
TL;DR: In this paper, the mechanism of dopant redistribution via out-diffusion and re-evaporation is described, which is essential for Ge-based electronics and optical applications.
Abstract: Heavily doped n-type Ge crystals are essential for Ge-based electronics and optical applications. In this report, we describe the mechanism of dopant redistribution via out-diffusion and re-evapora...

2 citations

Journal ArticleDOI
TL;DR: In this article, the structure of doubly transition metal doped silicon clusters M2Sin, M2Si18, NbMo, TaW were determined by DFT computations.

2 citations

Journal ArticleDOI
TL;DR: In this paper, the role of atomic hydrogen in Ge/Si core-shell nanowires with first-principles calculations was investigated and it was shown that the hole doping in the Ge-Si heterointerface is achievable through interstitial hydrogen mediated remote doping.
Abstract: We investigate the role of atomic hydrogen in Ge/Si core–shell nanowires with first-principles calculations and present that the hole doping in the Ge/Si heterointerface is achievable through interstitial hydrogen mediated remote doping. This atomic hydrogen induced hole doping could generate one-dimensional hole gas in Ge/Si core–shell nanowires. Hydrogen prefers to be incorporated in the Si shell due to the lattice strain effect. As the charge transition energy level of the interstitial hydrogen in Si is lower than the valence band maximum of the Ge band, the electrons in the Ge core prefer to move toward the Si shell and become trapped by the interstitial hydrogen. This unique hydrogen energy level in the Ge/Si heterostructure between the Ge and Si valence band edges drives the electron transfer from the Ge core and induces holes states in the Ge core through remote hole doping. We also perform a quantum transport simulation and show that a high conductive hole channel in the Ge core can be generated w...

2 citations

Proceedings ArticleDOI
24 Nov 2014
TL;DR: In this paper, a method of engineering constant composition, single crystal, defect free SiGe-on-insulator grown by a rapid melt growth technique using tailored tree-like structures is described.
Abstract: We report a method of engineering constant composition, single crystal, defect free SiGe-on-insulator grown by a rapid melt growth technique using tailored tree-like structures. Branches emanating from the main SiGe strip act as Silicon “reservoirs” to prevent the usual gradation of the alloy composition. This technique enables multiple SiGe strips to be grown using the same single generic Ge deposition step, each with a different composition determined by the structural design. Using this technique, we envisage a silicon photonics platform for on-chip optical communications whereby both modulators and detectors can be fabricated with the same device design and therefore the same simple fabrication steps. This can be realised by exploiting the rapid melt growth SiGe composition engineering detailed in this paper to tune the bandgap of electro-absorption modulators for multi-channel links using wavelength division multiplexing, whilst simultaneously forming pure Ge photodetectors. This technology could open the way for a new multilayer photonic architecture or for extremely low power density, multi-channel on-chip optical communications by integrating the concept with the cascaded photonic crystal architecture demonstrated by Debnath et al.

2 citations


Cites background from "Academic and industry research prog..."

  • ...High quality Ge or silicon-germanium-on-insulator (SGOI) has many attractive properties for numerous applications in electronics and photonics such as electro-absorption modulators [2] and high mobility complementary metal-oxide semiconductor (CMOS) devices [3]....

    [...]

References
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Proceedings ArticleDOI
01 Dec 2007
TL;DR: In this paper, a 45 nm logic technology is described that for the first time incorporates high-k + metal gate transistors in a high volume manufacturing process, resulting in the highest drive currents yet reported for NMOS and PMOS.
Abstract: A 45 nm logic technology is described that for the first time incorporates high-k + metal gate transistors in a high volume manufacturing process. The transistors feature 1.0 nm EOT high-k gate dielectric, dual band edge workfunction metal gates and third generation strained silicon, resulting in the highest drive currents yet reported for NMOS and PMOS. The technology also features trench contact based local routing, 9 layers of copper interconnect with low-k ILD, low cost 193 nm dry patterning, and 100% Pb-free packaging. Process yield, performance and reliability are demonstrated on 153 Mb SRAM arrays with SRAM cell size of 0.346 mum2, and on multiple microprocessors.

973 citations

Proceedings ArticleDOI
08 Dec 2003
TL;DR: In this article, the authors describe a novel strained transistor architecture which is incorporated into a 90nm logic technology on 300mm wafers, which features an epitaxially grown strained SiGe film embedded in the source drain regions.
Abstract: This paper describes the details of a novel strained transistor architecture which is incorporated into a 90nm logic technology on 300mm wafers The unique strained PMOS transistor structure features an epitaxially grown strained SiGe film embedded in the source drain regions Dramatic performance enhancement relative to unstrained devices are reported These transistors have gate length of 45nm and 50nm for NMOS and PMOS respectively, 12nm physical gate oxide and Ni salicide World record PMOS drive currents of 700/spl mu/A//spl mu/m (high V/sub T/) and 800/spl mu/A//spl mu/m (low V/sub T/) at 12V are demonstrated NMOS devices exercise a highly tensile silicon nitride capping layer to induce tensile strain in the NMOS channel region High NMOS drive currents of 126mA//spl mu/m (high VT) and 145mA//spl mu/m (low VT) at 12V are reported The technology is mature and is being ramped into high volume manufacturing to fabricate next generation Pentium/spl reg/ and Intel/spl reg/ Centrino/spl trade/ processor families

729 citations

Journal ArticleDOI
TL;DR: In this paper, a method of controlling threading dislocation densities in Ge on Si involving graded SiGe layers and chemical-mechanical polishing (CMP) is presented.
Abstract: A method of controlling threading dislocation densities in Ge on Si involving graded SiGe layers and chemical-mechanical polishing (CMP) is presented. This method has allowed us to grow a relaxed graded buffer to 100% Ge without the increase in threading dislocation density normally observed in thick graded structures. This sample has been characterized by transmission electron microscopy, etch-pit density, atomic force microscopy, Nomarski optical microscopy, and triple-axis x-ray diffraction. Compared to other relaxed graded buffers in which CMP was not implemented, this sample exhibits improvements in threading dislocation density and surface roughness. We have also made process modifications in order to eliminate particles due to gas-phase nucleation and cracks due to thermal mismatch strain. We have achieved relaxed Ge on Si with a threading dislocation density of 2.1×106 cm−2, and we expect that further process refinements will lead to lower threading dislocation densities on the order of bulk Ge su...

620 citations

Journal ArticleDOI
Yoshiki Kamata1
TL;DR: In this article, the opportunities and challenges of high-k/Ge MOSFETs are discussed on the basis of the material properties of Ge oxide to provide insights for future progress.

443 citations