Academic and industry research progress in germanium nanodevices
TL;DR: Germanium-based transistors have the potential to operate at high speeds with low power requirements and might therefore be used in non-silicon-based semiconductor technology in the future.
Abstract: Silicon has enabled the rise of the semiconductor electronics industry, but it was not the first material used in such devices. During the 1950s, just after the birth of the transistor, solid-state devices were almost exclusively manufactured from germanium. Today, one of the key ways to improve transistor performance is to increase charge-carrier mobility within the device channel. Motivated by this, the solid-state device research community is returning to investigating the high-mobility material germanium. Germanium-based transistors have the potential to operate at high speeds with low power requirements and might therefore be used in non-silicon-based semiconductor technology in the future.
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TL;DR: In this paper, the authors demonstrate the crystallization of the microstrips of electrodeposited amorphous germanium (Ge) on graphene on insulator by rapid melting growth for the first time.
2 citations
TL;DR: In this article , the molecular and electronic properties of Sc-doped germanium anion clusters were explored via quantum chemistry calculations using mPW2PLYP scheme and unprejudiced structural searching technique ABCluster.
Abstract: A comparison of theoretical and experimental properties is the most effective strategy for determining the global minimum (GM) because there is no experimental method to directly test the GM structure of clusters by now. The molecular and electronic structures and properties of Sc-doped germanium anion clusters were explored via quantum chemistry calculations using mPW2PLYP scheme and unprejudiced structural searching technique ABCluster. Isomers are determined by ABCluster structural searches, followed by reoptimization of a great number of candidate geometries. The simulated photoelectron spectra for the GM structures match with those measured in experiment, suggesting that the current most stable structures are existence in the experiment. The molecular structural evolution modes appear as follows: as the cluster size n increases, the growth patterns are from the Sc-linked geometry (n = 10, 11) in which the Sc atom acts as a linker (Sc atom connects two Ge sub-clusters) to the Sc-encapsulated form (n = 13–17) in which the Sc atom is settled in the core of the Ge-cage framework. Besides, the properties including stability, HOMO-LUMO gap, charge transfer, IR, Raman, and UV–Vis spectra were calculated. The Raman spectra are red-shifted from the Sc-linked to Sc-encapsulated configurations. The analyses of stability, HOMO-LUMO gap, and UV–Vis spectra revealed that the ScGe16− nanocluster could be the most suitable building block for further development as potential optoelectronic materials such as solar cell.
2 citations
Dissertation•
01 Jan 2013
TL;DR: In this article, a low temperature nickel process has been developed that produces Ohmic contacts to n-Ge with a specific contact resistivity of, which is attributed to the low resistivity NiGe phase, which was identified using electron diffraction in a transmission electron microscope.
Abstract: There is presently increased interest in using germanium (Ge) for both electronic and optical devices on top of silicon (Si) substrates to expand the functionality of Si technology. It has been extremely difficult to form an Ohmic contact to n-Ge due to Fermi level pinning just above the Valence band. A low temperature nickel process has been developed that produces Ohmic contacts to n-Ge with a specific contact resistivity of , which to date is a record. The low contact resistivity is attributed to the low resistivity NiGe phase, which was identified using electron diffraction in a transmission electron microscope. Light emission from Ge light emitting diodes (LEDs) was investigated. Ge is an indirect bandgap semiconductor but the difference in energy between the direct and indirect is small (~136 meV), through a combination of n-type doping and tensile strain, the band structure can be engineered to produce a more direct bandgap material. A silicon nitride (Si3N4) process has been developed that imparts tensile strain into the Ge. The stress in the Si3N4 film can be controlled by the RF power used during the plasma enhanced chemical vapour deposition. LEDs covered with Si3N4 stressors were characterised by Fourier transform infrared spectroscopy. Electroluminescence characterisation (EL) revealed that the peak position of the direct and indirect radiative transitions did not vary with the Si3N4 stressors due to the device geometries being too large. Therefore, nanostructures consisting of pillars smaller than a micron were investigated. Photoluminescence characterisation of 100 nm Ge pillars with Si3N4 stressors show emission at much longer wavelengths compared to bulk Ge (> 2.2 μm). In addition, the EL from Ge quantum wells grown on Si was also investigated. EL characterisation demonstrates two peaks around 1.55 and 1.8 μm, which corresponds to the radiative recombination between the direct and indirect transitions, respectively. This result is the first demonstration of EL above 1.45 μm for Ge quantum wells. Finally, the fabrication of Ge-on-Si single-photon avalanche detectors are presented. A single-photon detection efficiency of 4 % at 1310 nm wavelength was measured at low temperature (100 K). The devices have the lowest reported noise equivalent power for a Ge-on-Si single-photon avalanche detector (1×10-14 WHz-1/2).
2 citations
TL;DR: In this paper, the authors use first principles simulations to engineer Ge nanofins for maximum hole mobility by controlling strain tri-axially through nano-patterning, and show that the transverse strain relaxation resulting from the reduction in the aspect ratio of the fins leads to a significant enhancement in phonon limited hole mobility (7× over unstrained, bulk Ge and 3.5× over biaxially strained Ge).
Abstract: We use first principles simulations to engineer Ge nanofins for maximum hole mobility by controlling strain tri-axially through nano-patterning. Large-scale molecular dynamics predict fully relaxed, atomic structures for experimentally achievable nanofins, and orthogonal tight binding is used to obtain the corresponding electronic structure. Hole transport properties are then obtained via a linearized Boltzmann formalism. This approach explicitly accounts for free surfaces and associated strain relaxation as well as strain gradients which are critical for quantitative predictions in nanoscale structures. We show that the transverse strain relaxation resulting from the reduction in the aspect ratio of the fins leads to a significant enhancement in phonon limited hole mobility (7× over unstrained, bulk Ge, and 3.5× over biaxially strained Ge). Maximum enhancement is achieved by reducing the width to be approximately 1.5 times the height and further reduction in width does not result in additional gains. These results indicate significant room for improvement over current-generation Ge nanofins, provide geometrical guidelines to design optimized geometries and insight into the physics behind the significant mobility enhancement.
2 citations
TL;DR: In this paper , the structure of doubly transition metal doped silicon clusters M2Sin, M2 = Mo2, Nb2, Ta2, W2, nbMo, TaW were determined by DFT computations.
Abstract: Geometries of doubly transition metal doped silicon clusters M2Sin, M2 = Mo2, Nb2, Ta2, W2, NbMo, TaW were determined by DFT computations. Geometries of M2Sin in the range from 11 to 18 Si atoms change from a tubular shape to a cage and then a fused cage. The M2Si18 sizes present us with a novel structural motif, the fused cage, for silicon clusters. Such fused cages arise from a fusion of both MSi10 and MSi12 prisms followed by addition of two Si atoms. Formation and filling of electron shells contribute to the high thermodynamic stability of M2Si18 fused clusters.
2 citations
References
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01 Dec 2007
TL;DR: In this paper, a 45 nm logic technology is described that for the first time incorporates high-k + metal gate transistors in a high volume manufacturing process, resulting in the highest drive currents yet reported for NMOS and PMOS.
Abstract: A 45 nm logic technology is described that for the first time incorporates high-k + metal gate transistors in a high volume manufacturing process. The transistors feature 1.0 nm EOT high-k gate dielectric, dual band edge workfunction metal gates and third generation strained silicon, resulting in the highest drive currents yet reported for NMOS and PMOS. The technology also features trench contact based local routing, 9 layers of copper interconnect with low-k ILD, low cost 193 nm dry patterning, and 100% Pb-free packaging. Process yield, performance and reliability are demonstrated on 153 Mb SRAM arrays with SRAM cell size of 0.346 mum2, and on multiple microprocessors.
973 citations
08 Dec 2003
TL;DR: In this article, the authors describe a novel strained transistor architecture which is incorporated into a 90nm logic technology on 300mm wafers, which features an epitaxially grown strained SiGe film embedded in the source drain regions.
Abstract: This paper describes the details of a novel strained transistor architecture which is incorporated into a 90nm logic technology on 300mm wafers The unique strained PMOS transistor structure features an epitaxially grown strained SiGe film embedded in the source drain regions Dramatic performance enhancement relative to unstrained devices are reported These transistors have gate length of 45nm and 50nm for NMOS and PMOS respectively, 12nm physical gate oxide and Ni salicide World record PMOS drive currents of 700/spl mu/A//spl mu/m (high V/sub T/) and 800/spl mu/A//spl mu/m (low V/sub T/) at 12V are demonstrated NMOS devices exercise a highly tensile silicon nitride capping layer to induce tensile strain in the NMOS channel region High NMOS drive currents of 126mA//spl mu/m (high VT) and 145mA//spl mu/m (low VT) at 12V are reported The technology is mature and is being ramped into high volume manufacturing to fabricate next generation Pentium/spl reg/ and Intel/spl reg/ Centrino/spl trade/ processor families
729 citations
TL;DR: In this paper, a method of controlling threading dislocation densities in Ge on Si involving graded SiGe layers and chemical-mechanical polishing (CMP) is presented.
Abstract: A method of controlling threading dislocation densities in Ge on Si involving graded SiGe layers and chemical-mechanical polishing (CMP) is presented. This method has allowed us to grow a relaxed graded buffer to 100% Ge without the increase in threading dislocation density normally observed in thick graded structures. This sample has been characterized by transmission electron microscopy, etch-pit density, atomic force microscopy, Nomarski optical microscopy, and triple-axis x-ray diffraction. Compared to other relaxed graded buffers in which CMP was not implemented, this sample exhibits improvements in threading dislocation density and surface roughness. We have also made process modifications in order to eliminate particles due to gas-phase nucleation and cracks due to thermal mismatch strain. We have achieved relaxed Ge on Si with a threading dislocation density of 2.1×106 cm−2, and we expect that further process refinements will lead to lower threading dislocation densities on the order of bulk Ge su...
620 citations
TL;DR: In this article, the opportunities and challenges of high-k/Ge MOSFETs are discussed on the basis of the material properties of Ge oxide to provide insights for future progress.
443 citations