Academic and industry research progress in germanium nanodevices
TL;DR: Germanium-based transistors have the potential to operate at high speeds with low power requirements and might therefore be used in non-silicon-based semiconductor technology in the future.
Abstract: Silicon has enabled the rise of the semiconductor electronics industry, but it was not the first material used in such devices. During the 1950s, just after the birth of the transistor, solid-state devices were almost exclusively manufactured from germanium. Today, one of the key ways to improve transistor performance is to increase charge-carrier mobility within the device channel. Motivated by this, the solid-state device research community is returning to investigating the high-mobility material germanium. Germanium-based transistors have the potential to operate at high speeds with low power requirements and might therefore be used in non-silicon-based semiconductor technology in the future.
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TL;DR: In this paper, an electrical doping method to realize the high n-type doping for a germanium (Ge) layer in a low-doped N-type Ge metal-oxide-semiconductor (MOS) structure in the accumulation condition is proposed, which maintains the initial crystal quality of Ge.
Abstract: In this article, an electrical doping method to realize the high n-type doping for a germanium (Ge) layer in a low-doped n-type Ge metal-oxide-semiconductor (MOS) structure in the accumulation condition is proposed, which maintains the initial crystal quality of Ge. The direct-bandgap electroluminescence (EL) from Ge light-emitting diode (LED) has been demonstrated with 1.5– $1.6~\mu \text{m}$ infrared emission using the metal/graphene/high- ${k}$ / interfacial layer (IL)/ ${n}$ -Ge MOS structure fabricated on bulk-Ge substrate. An onset current density of 5 A cm−2 is observed, which is, up to now, the lowest onset current density compared with the Ge LEDs fabricated on unstrained Ge substrates. These results indicate the superiority of the electrical doping method and the interface passivation technique on yielding the high-performance Ge-based LEDs and lasers.
1 citations
Cites background or methods from "Academic and industry research prog..."
...(MOS) field-effect transistors (FETs) [5], [6]....
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...Unfortunately, it is difficult to obtain the high-quality Ge MOS structure with low density of interface traps (Dit) due to the instability of the Ge surface and the lack of naturally stable dielectric GeO2 [5], [6]....
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...sistor was based on Ge, as was the first integrated circuit [5]....
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...The thicknesses of each layer are indicated as: Au: 55 nm, Cr: 5 nm, graphene: monolayer, Al2O3: 5 nm, GeO2 IL: 0.5 nm, Ge: 500 μm, and Al: 100 nm. Fig....
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TL;DR: In this article, the authors theoretically reproduce the experimental data for conventional group IV and III-V semiconductors without involving adjustable parameters by curing the shortcoming of classical models, and propose design principles for semiconducting materials towards high hole mobility.
Abstract: Si dominates the semiconductor industry material but possesses an abnormally low room temperature hole mobility (505 cm^2/Vs), which is four times lower than that of Diamond and Ge (2000 cm^2/Vs), two adjacent neighbours in the group IV column in the Periodic Table. In the past half-century, extensive efforts have been made to overcome the challenges of Si technology caused by low mobility in Si. However, the fundamental understanding of the underlying mechanisms remains lacking. Here, we theoretically reproduce the experimental data for conventional group IV and III-V semiconductors without involving adjustable parameters by curing the shortcoming of classical models. We uncover that the abnormally low hole mobility in Si originating from a combination of the strong interband scattering resulting from its weak spin-orbit coupling and the intensive participation of optical phonons in hole-phonon scattering. In contrast, the strong spin-orbit coupling in Ge leads to a negligible interband scattering; the strong bond and light atom mass in diamond give rise to high optical phonons frequency, preventing their participation in scattering. Based on these understandings rooted into the fundamental atomic properties, we present design principles for semiconducting materials towards high hole mobility.
1 citations
Cites background from "Academic and industry research prog..."
...It stimulates tremendous efforts in past decades in seeking materials with high hole mobility to replace Si to substantially improve PMOS device performance to maximize microchip performance gains [7]....
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...Specifically, increasing carrier mobility can enhance the transistor drive current, which can, in turn, improve device performance or maintain performance and reduce power consumption [7]....
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...However, the corresponding hole mobility in III-V semiconductors is orders of magnitude lower due to their considerably larger valence-band effective mass, together with their much shorter scattering time for hole transport than for electron transport [7]....
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...Because the hole mobility (μh = 505 cm (2)/Vs) is significantly lower than the electron mobility (μ2 = 1450 cm (2)/Vs) in Si [7, 8], the device performance of p-type transistor (PMOS) operates only at about one third the performance of n-type transistor (NMOS) [9]....
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TL;DR: In this article , the authors present high performance, vertical nanowire gate-all-around FETs based on the GeSn-material system grown on Si, which enables high mobility channel materials for improved device performance at low power levels.
Abstract: Abstract The continued downscaling of silicon CMOS technology presents challenges for achieving the required low power consumption. While high mobility channel materials hold promise for improved device performance at low power levels, a material system which enables both high mobility n-FETs and p-FETs, that is compatible with Si technology and can be readily integrated into existing fabrication lines is required. Here, we present high performance, vertical nanowire gate-all-around FETs based on the GeSn-material system grown on Si. While the p-FET transconductance is increased to 850 µS/µm by exploiting the small band gap of GeSn as source yielding high injection velocities, the mobility in n-FETs is increased 2.5-fold compared to a Ge reference device, by using GeSn as channel material. The potential of the material system for a future beyond Si CMOS logic and quantum computing applications is demonstrated via a GeSn inverter and steep switching at cryogenic temperatures, respectively.
1 citations
TL;DR: In this paper , the authors reported the synthesis of a stable plumbylone by reduction of a bromodigermylplumbylene (2) with 2.2 equiv.
Abstract: We report herein the synthesis of a stable plumbylone (3) by reduction of a bromodigermylplumbylene (2) with 2.2 equiv. of potassium graphite (KC8). The molecular structure of 3 was established by a single-crystal X-ray diffraction study and features a two-coordinated Pb center with an acute Ge-Pb-Ge bond angle. Computational studies showed that this complex (3) possesses a singlet electronic ground state with a Pb(0) center. Its high thermal stability can be most likely ascribed to the delocalization of π electrons over the Ge-Pb-Ge moiety. A preliminary reactivity study demonstrates that complex 3 can deliver Pb(0) atoms to an organic azide producing a tetrameric imido complex [(PbNDipp)4] (Dipp = 2,6- iPr-C6H3, 4) and perform a metathesis reaction with GeCl2·dioxane to produce a bis(germylene)-stabilized germylone (5), highlighting the synthetic utility of 3.
1 citations
TL;DR: In this article, an efficient passivation strategy for this semiconductor is still a challenge and an efficient O2 passivation in O2 of metal/dielectric sta...
Abstract: Ge is a promising material to improve transistor performance. However, finding an efficient passivation strategy for this semiconductor is still a challenge. Annealing in O2 of metal/dielectric sta...
1 citations
References
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01 Dec 2007
TL;DR: In this paper, a 45 nm logic technology is described that for the first time incorporates high-k + metal gate transistors in a high volume manufacturing process, resulting in the highest drive currents yet reported for NMOS and PMOS.
Abstract: A 45 nm logic technology is described that for the first time incorporates high-k + metal gate transistors in a high volume manufacturing process. The transistors feature 1.0 nm EOT high-k gate dielectric, dual band edge workfunction metal gates and third generation strained silicon, resulting in the highest drive currents yet reported for NMOS and PMOS. The technology also features trench contact based local routing, 9 layers of copper interconnect with low-k ILD, low cost 193 nm dry patterning, and 100% Pb-free packaging. Process yield, performance and reliability are demonstrated on 153 Mb SRAM arrays with SRAM cell size of 0.346 mum2, and on multiple microprocessors.
973 citations
08 Dec 2003
TL;DR: In this article, the authors describe a novel strained transistor architecture which is incorporated into a 90nm logic technology on 300mm wafers, which features an epitaxially grown strained SiGe film embedded in the source drain regions.
Abstract: This paper describes the details of a novel strained transistor architecture which is incorporated into a 90nm logic technology on 300mm wafers The unique strained PMOS transistor structure features an epitaxially grown strained SiGe film embedded in the source drain regions Dramatic performance enhancement relative to unstrained devices are reported These transistors have gate length of 45nm and 50nm for NMOS and PMOS respectively, 12nm physical gate oxide and Ni salicide World record PMOS drive currents of 700/spl mu/A//spl mu/m (high V/sub T/) and 800/spl mu/A//spl mu/m (low V/sub T/) at 12V are demonstrated NMOS devices exercise a highly tensile silicon nitride capping layer to induce tensile strain in the NMOS channel region High NMOS drive currents of 126mA//spl mu/m (high VT) and 145mA//spl mu/m (low VT) at 12V are reported The technology is mature and is being ramped into high volume manufacturing to fabricate next generation Pentium/spl reg/ and Intel/spl reg/ Centrino/spl trade/ processor families
729 citations
TL;DR: In this paper, a method of controlling threading dislocation densities in Ge on Si involving graded SiGe layers and chemical-mechanical polishing (CMP) is presented.
Abstract: A method of controlling threading dislocation densities in Ge on Si involving graded SiGe layers and chemical-mechanical polishing (CMP) is presented. This method has allowed us to grow a relaxed graded buffer to 100% Ge without the increase in threading dislocation density normally observed in thick graded structures. This sample has been characterized by transmission electron microscopy, etch-pit density, atomic force microscopy, Nomarski optical microscopy, and triple-axis x-ray diffraction. Compared to other relaxed graded buffers in which CMP was not implemented, this sample exhibits improvements in threading dislocation density and surface roughness. We have also made process modifications in order to eliminate particles due to gas-phase nucleation and cracks due to thermal mismatch strain. We have achieved relaxed Ge on Si with a threading dislocation density of 2.1×106 cm−2, and we expect that further process refinements will lead to lower threading dislocation densities on the order of bulk Ge su...
620 citations
TL;DR: In this article, the opportunities and challenges of high-k/Ge MOSFETs are discussed on the basis of the material properties of Ge oxide to provide insights for future progress.
443 citations