Academic and industry research progress in germanium nanodevices
TL;DR: Germanium-based transistors have the potential to operate at high speeds with low power requirements and might therefore be used in non-silicon-based semiconductor technology in the future.
Abstract: Silicon has enabled the rise of the semiconductor electronics industry, but it was not the first material used in such devices. During the 1950s, just after the birth of the transistor, solid-state devices were almost exclusively manufactured from germanium. Today, one of the key ways to improve transistor performance is to increase charge-carrier mobility within the device channel. Motivated by this, the solid-state device research community is returning to investigating the high-mobility material germanium. Germanium-based transistors have the potential to operate at high speeds with low power requirements and might therefore be used in non-silicon-based semiconductor technology in the future.
Citations
More filters
TL;DR: In this article, the thermal transport properties of Al2O3 films on Ge substrates using the thermo-reflectance method were measured and the thermal conductivity кm of the Al 2O3 and Ge interfaces were estimated to be 0.83 w −m−m−1 K−1 and 2.8 w −w −m −1 K −1, respectively.
1 citations
01 Jan 2016
TL;DR: In this paper, the analysis of the dynamics of intrinsic point defects in single crystal germanium is presented, which relates technological process parameters with microdefect formation in a single crystal Germanium.
Abstract: The knowledge of the dynamics of intrinsic point defects, is essential for controlling and engineering their formation and clustering and thus also the quality of the germanium crystals used for producing germanium wafers for space solar cells and terrestrial concentrator photovoltaic, as well as of the active layer of germanium in complementary metal-oxide semiconductors technology. The analyses presented in this paper relate technological process parameters with microdefect formation in single crystal germanium.
1 citations
TL;DR: In this paper, the effect of traps and defects on high temperature performance of p-type germanium-on-insulator (GOI) based junctionless nanowire transistors (JNTs) at temperatures ranging from 300 to 450 K was investigated.
Abstract: We investigate the effect of traps and defects on high temperature performance of p-type germanium-on-insulator (GOI) based junctionless nanowire transistors (JNTs) at temperatures ranging from 300 to 450 K. Temperature dependence of the main electrical parameters, such as drive current (Ion), leakage current (Ioff), threshold voltage (Vt), transconductance (Gm) and subthreshold slope (SS) are extracted and compared with the reported results of conventional inversion mode (IM) MOSFETs and Si based JNTs. The results show that the high interface trap density (Dit) and defects can degrade high temperature reliability of GOI based JNTs significantly, in terms of Ioff, Vt variation, Gm-max and SS values. The Ioff is much more dependent on temperature than Ion and mainly affected by trap-assisted-tunneling (TAT) current. The Vt variation with temperature is larger than that for IM MOSFETs and SOI based JNTs, which can be mostly attributed to the high Dit. The high Dit can also induce high SS values. The maximum Gm has a weak dependence on temperature and is significantly influenced by neutral defects scattering. Limiting the Dit and neutral defect densities is critical for the reliability of GOI based JNTs working at high temperatures.
1 citations
01 Jan 2000
TL;DR: In this paper, the authors reported a two dimensional hole gas system in pure germanium channels, where the hole mobility is limited by roughness scattering at the alloy-Ge interface at low temperatures and by parallel conduction at high temperatures.
Abstract: Recently there has been a lot of interest in two dimensional hole gas systems in pure germanium channels, since Ge has the highest intrinsic bulk hole mobility of all the commonly employed semiconductors, being comparable to the electron mobilites in bulk Si. Konig et. al. [l] have reported a maximum extrinsic transconductance of 125mS/mm(290mS/mm) at 300K(77K) in these Ge channel FETs. However, the hole mobility achieved in these systems are limited by roughness scattering at the alloy-Ge interface at low temperatures and by parallel conduction at high temperatures. Engelhardt et. al. [2] have reported a maximum hole mobility of $1300cm^2/Vs$ at room temperature with the channel density changing by about 50% from 4.2K to 300K, indicating the presence of parallel conduction.
1 citations
TL;DR: The structural growth of Gd-doped germanium anionic nanoclusters, GdGen− (n = 5−18), has been explored via quantum chemistry calculations using the mPW2PLYP method and an unprejudiced structural searching technique known as ABCluster as mentioned in this paper .
Abstract: The structural growth of Gd-doped germanium anionic nanoclusters, GdGen− (n = 5–18), has been explored via quantum chemistry calculations using the mPW2PLYP method and an unprejudiced structural searching technique known as ABCluster. The optimized geometries exhibited that when n = 10–14, the structural evolution favors the Gd-linked configuration where the Gd atom as a connector bridges two Ge subgroups, while the Gd atom is encapsulated in a closed cage-like Ge frame when n = 15–18. The properties like magnetic moment, charge transfer, relative stability, HOMO–LUMO gap, photoelectron spectra, and infrared and Raman spectra have been predicted. The information of these spectra could provide extra approaches to experimentally determine the electronic structures and equilibrium configuration of these compounds. The largest spin magnetic moment of 7 μB is attained via half-filled 4f states. The GdGe16− nanocluster is determined to be a superatom because its total valence of 75 electrons can be distributed to the orbital sequence of 1S21P6(4f7)1D101F142S22P21G182P42D10, which complies with not only Hund's rule, but also the spherical jellium model. Particularly, its UV-Vis spectra match well with solar energy distribution. Such materials act as nano multifunctional building units potentially used in solar energy converters or ultra-highly sensitive near-infrared photodetectors.
1 citations
References
More filters
01 Dec 2007
TL;DR: In this paper, a 45 nm logic technology is described that for the first time incorporates high-k + metal gate transistors in a high volume manufacturing process, resulting in the highest drive currents yet reported for NMOS and PMOS.
Abstract: A 45 nm logic technology is described that for the first time incorporates high-k + metal gate transistors in a high volume manufacturing process. The transistors feature 1.0 nm EOT high-k gate dielectric, dual band edge workfunction metal gates and third generation strained silicon, resulting in the highest drive currents yet reported for NMOS and PMOS. The technology also features trench contact based local routing, 9 layers of copper interconnect with low-k ILD, low cost 193 nm dry patterning, and 100% Pb-free packaging. Process yield, performance and reliability are demonstrated on 153 Mb SRAM arrays with SRAM cell size of 0.346 mum2, and on multiple microprocessors.
973 citations
08 Dec 2003
TL;DR: In this article, the authors describe a novel strained transistor architecture which is incorporated into a 90nm logic technology on 300mm wafers, which features an epitaxially grown strained SiGe film embedded in the source drain regions.
Abstract: This paper describes the details of a novel strained transistor architecture which is incorporated into a 90nm logic technology on 300mm wafers The unique strained PMOS transistor structure features an epitaxially grown strained SiGe film embedded in the source drain regions Dramatic performance enhancement relative to unstrained devices are reported These transistors have gate length of 45nm and 50nm for NMOS and PMOS respectively, 12nm physical gate oxide and Ni salicide World record PMOS drive currents of 700/spl mu/A//spl mu/m (high V/sub T/) and 800/spl mu/A//spl mu/m (low V/sub T/) at 12V are demonstrated NMOS devices exercise a highly tensile silicon nitride capping layer to induce tensile strain in the NMOS channel region High NMOS drive currents of 126mA//spl mu/m (high VT) and 145mA//spl mu/m (low VT) at 12V are reported The technology is mature and is being ramped into high volume manufacturing to fabricate next generation Pentium/spl reg/ and Intel/spl reg/ Centrino/spl trade/ processor families
729 citations
TL;DR: In this paper, a method of controlling threading dislocation densities in Ge on Si involving graded SiGe layers and chemical-mechanical polishing (CMP) is presented.
Abstract: A method of controlling threading dislocation densities in Ge on Si involving graded SiGe layers and chemical-mechanical polishing (CMP) is presented. This method has allowed us to grow a relaxed graded buffer to 100% Ge without the increase in threading dislocation density normally observed in thick graded structures. This sample has been characterized by transmission electron microscopy, etch-pit density, atomic force microscopy, Nomarski optical microscopy, and triple-axis x-ray diffraction. Compared to other relaxed graded buffers in which CMP was not implemented, this sample exhibits improvements in threading dislocation density and surface roughness. We have also made process modifications in order to eliminate particles due to gas-phase nucleation and cracks due to thermal mismatch strain. We have achieved relaxed Ge on Si with a threading dislocation density of 2.1×106 cm−2, and we expect that further process refinements will lead to lower threading dislocation densities on the order of bulk Ge su...
620 citations
TL;DR: In this article, the opportunities and challenges of high-k/Ge MOSFETs are discussed on the basis of the material properties of Ge oxide to provide insights for future progress.
443 citations