Academic and industry research progress in germanium nanodevices
TL;DR: Germanium-based transistors have the potential to operate at high speeds with low power requirements and might therefore be used in non-silicon-based semiconductor technology in the future.
Abstract: Silicon has enabled the rise of the semiconductor electronics industry, but it was not the first material used in such devices. During the 1950s, just after the birth of the transistor, solid-state devices were almost exclusively manufactured from germanium. Today, one of the key ways to improve transistor performance is to increase charge-carrier mobility within the device channel. Motivated by this, the solid-state device research community is returning to investigating the high-mobility material germanium. Germanium-based transistors have the potential to operate at high speeds with low power requirements and might therefore be used in non-silicon-based semiconductor technology in the future.
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01 Jan 2018
TL;DR: A solution-phase synthesis of nickel germanide nanocrystals was developed to produce colloidal particles possessing an unexpected Ni¬19Ge12 crystal phase as discussed by the authors, but the use of a trioctylphosphine cosolvent allowed formation of a Ni1Ge1 phase that was not thermally stable.
Abstract: Author(s): Dupper, Torin Joseph | Advisor(s): Hochbaum, Allon I | Abstract: The colloidal synthesis and surface modification of germanium and germanium-based nanomaterials is a developing area of research with potential applications in a variety of fields. Colloidal germanium nanocrystal syntheses have improved significantly in recent years, but there has been little exploration into the synthesis of Ge-based nanomaterials, especially metal-germanium nanocrystals. A solution-phase synthesis of nickel germanide nanocrystals was developed to produce colloidal particles possessing an unexpected Ni¬19Ge12 crystal phase. The mechanism of this synthesis was explored to show that the Ni19Ge12 phase formed over a wide range of experimental conditions, but the use of a trioctylphosphine cosolvent allowed formation of a Ni1Ge1 phase that was not thermally stable. Many proposed applications of colloidal Ge nanocrystals require thorough particle surface modification. To this end, surface ligand exchange of Ge nanocrystals was examined and improved through the development of a high-temperature sulfur treatment. Finally, Ge nanocrystal films were cast from solution and their electrical conductivity was characterized.
1 citations
TL;DR: In this article, a facile approach to produce biaxially strained germanium micro-dot arrays by hydrogen ion implantation is described, which is compatible with metal-oxide-semiconductor processing can be extended to strain engineering in wafer scale.
Abstract: Although strain engineering is an effective method to modify the bandgap of germanium for germanium-based microelectronic, the introduction of biaxial tensile strain with a particular pattern to germanium is challenging. Herein, a facile approach to produce biaxially strained germanium micro-dot arrays by hydrogen ion implantation is described. By changing the ion implantation and annealing conditions, the morphology of the micro-dots can be optimized and the biaxially tensile strain can be tuned to a maximum value of 0.6%. This method which is compatible with mainstream complementary metal-oxide-semiconductor processing can be extended to strain engineering in wafer scale.
1 citations
Cites background from "Academic and industry research prog..."
...Germanium (Ge) has been widely explored for optical and electronic applications because of the high hole mobility [1] and compatibility with mainstream integrated circuit technology....
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TL;DR: The results demonstrate that the miscut substrates offer a promising degree of freedom for the feasible modification of self-assembled nanostructures.
Abstract: Self-assembled GeSi nanostructures on miscut Si(001) substrates are studied systematically with regard to the miscut angle and azimuth, the amount of Ge and the growth temperature. The comprehensive dependence of the spatial arrangement, which can exhibit one- and two-dimensional (1D and 2D) ordering, as well as the shape and density, of GeSi nanostructures on the miscut angle is observed. The orientation and side-walls of the 1D ordered in-plane GeSi nanowires on miscut Si(001) substrates are intimately associated with the miscut azimuth towards the 〈110〉 or 〈010〉 directions. Furthermore, the unique evolution of the GeSi nanostructures with the amount of Ge and the growth temperature on miscut Si (001) substrates towards the 〈010〉 direction is discovered. Such promising features of self-assembled GeSi nanostructures on miscut Si (001) substrates are explained in terms of the thermodynamics and growth kinetics, which are both affected significantly by the substrate vicinality. These results demonstrate that the miscut substrates offer a promising degree of freedom for the feasible modification of self-assembled nanostructures.
1 citations
TL;DR: In this article, the pristine Ge(0,0,1) surface is shown to conduct at room temperature by using temperature-dependent angle-resolved photoelectron spectroscopy, scanning tunneling microscopy and first principles calculations.
1 citations
Dissertation•
23 Jun 2016
TL;DR: Nguyen et al. as mentioned in this paper investigated the structural characteristics of the Ge epitaxial layer heterogeneously integrated on Si using a composite III-V AlAs/GaAs buffer and the electrical characteristics of MOS capacitors (MOS-C's) fabricated on the aforementioned stack.
Abstract: Over the past four decades, aggressive scaling of silicon (Si) based complementary metal-oxide-semiconductor (CMOS) transistors has resulted in an exponential increase in device density, and thus an exponential increase in computing power. Increasing transistor density also results in increasing total power consumption and thus, necessitates supply voltage scaling in order to maintain low-power device operation. However, with increased supply voltage scaling, transistor drive current is significantly degraded due to the low carrier mobility of Si. To overcome the key challenges of device and voltage scaling required for low-power electronic operation without the degradation of transistor drive current requires the adoption of narrow bandgap channel materials with superior transport properties. However, the use of such materials as bulk substrates remains cost-prohibitive. Thus, another key challenge lies in the heterogeneous integration of high-mobility channel materials on affordable, established Si platform. Germanium (Ge) is an attractive candidate for next-generation low-power devices owing to its high electron and high hole mobility. Recently, AlAs/GaAs epilayers were demonstrated as a potential buffer platform for nextgeneration Ge-based electronics integrated on Si substrate. This research systematically investigates the structural characteristics of the Ge epitaxial layer heterogeneously integrated on Si using a composite III-V AlAs/GaAs buffer and the electrical characteristics of MOS capacitors (MOS-C’s) fabricated on the aforementioned stack. Further passivation techniques and interface engineering is then pursued on MOS-C’s fabricated from (100) and (110) crystallographically oriented epitaxial Ge integrated on AlAs/GaAs material stacks, balancing out effective oxide thickness (EOT) and reduction of oxide and interfacial traps in order to ensure a pristine interfacial quality for highperformance electronic applications. Further, work function tuning is demonstrated for the first time on the different crystallographically oriented epitaxial Ge integrated on AlAs/GaAs material stacks using two different gate metals, demonstrating the tunability of threshold voltage, VTH, required for transistor applications. The research demonstrates the feasibility of future high-mobility channel material integration on Si via large bandgap buffer architectures for high-speed, low-power, high-performance CMOS logic applications. Heteroepitaxial Ge on Si via High-Bandgap III-V Buffers for Low-Power Electronic Applications Peter D. Nguyen GENERAL AUDIENCE ABSTRACT Over the past four decades, the shrinking of silicon (Si) based complementary metaloxide-semiconductor (CMOS) transistors has allowed for a boost in electronic device performance, but also aggravates power consumption. To mitigate these power concerns, the industry is looking to switch over from silicon-based transistors to those that are alternative material based. A possible alternative material solution is Germanium (Ge), which has inherent material characteristics that are attractive for low-power, high-speed electronic applications. However, the use of Ge as a bulk material for transistor fabrication is cost-prohibitive. Thus, to address cost concerns, the integration of Ge on to Si via a buffer layer “bridge” is necessary. Recently, AlAs/GaAs buffer layers were demonstrated as a potential buffer solution for next-generation Ge-based electronic devices integrated on to Si. This research systematically investigates the material characteristics of Ge layers integrated on Si using the AlAs/GaAs buffer layer approach, as well as MOS capacitors (MOS-C’s) fabricated on the aforementioned material stack. Furthermore, interface engineering is pursued on different crystallographically oriented Ge integrated on Si via the AlAs/GaAs buffer approach in order to refine the MOS capacitor devices in order to demonstrate the feasibility of the use of such material stacks for state-of-the-art FinFETs (Fin Field-Effect Transistors). Finally, the tunability of a key device characteristic known as threshold voltage, VTH, is demonstrated via the use of two different gate metals for the Ge-based MOS capacitor devices integrated on Si using AlAs/GaAs buffer layers. Thus, this research demonstrates the feasibility of the use of Ge integrated on Si via AlAs/GaAs buffer layers for high-speed, low-power electronic devices.
1 citations
References
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01 Dec 2007
TL;DR: In this paper, a 45 nm logic technology is described that for the first time incorporates high-k + metal gate transistors in a high volume manufacturing process, resulting in the highest drive currents yet reported for NMOS and PMOS.
Abstract: A 45 nm logic technology is described that for the first time incorporates high-k + metal gate transistors in a high volume manufacturing process. The transistors feature 1.0 nm EOT high-k gate dielectric, dual band edge workfunction metal gates and third generation strained silicon, resulting in the highest drive currents yet reported for NMOS and PMOS. The technology also features trench contact based local routing, 9 layers of copper interconnect with low-k ILD, low cost 193 nm dry patterning, and 100% Pb-free packaging. Process yield, performance and reliability are demonstrated on 153 Mb SRAM arrays with SRAM cell size of 0.346 mum2, and on multiple microprocessors.
973 citations
08 Dec 2003
TL;DR: In this article, the authors describe a novel strained transistor architecture which is incorporated into a 90nm logic technology on 300mm wafers, which features an epitaxially grown strained SiGe film embedded in the source drain regions.
Abstract: This paper describes the details of a novel strained transistor architecture which is incorporated into a 90nm logic technology on 300mm wafers The unique strained PMOS transistor structure features an epitaxially grown strained SiGe film embedded in the source drain regions Dramatic performance enhancement relative to unstrained devices are reported These transistors have gate length of 45nm and 50nm for NMOS and PMOS respectively, 12nm physical gate oxide and Ni salicide World record PMOS drive currents of 700/spl mu/A//spl mu/m (high V/sub T/) and 800/spl mu/A//spl mu/m (low V/sub T/) at 12V are demonstrated NMOS devices exercise a highly tensile silicon nitride capping layer to induce tensile strain in the NMOS channel region High NMOS drive currents of 126mA//spl mu/m (high VT) and 145mA//spl mu/m (low VT) at 12V are reported The technology is mature and is being ramped into high volume manufacturing to fabricate next generation Pentium/spl reg/ and Intel/spl reg/ Centrino/spl trade/ processor families
729 citations
TL;DR: In this paper, a method of controlling threading dislocation densities in Ge on Si involving graded SiGe layers and chemical-mechanical polishing (CMP) is presented.
Abstract: A method of controlling threading dislocation densities in Ge on Si involving graded SiGe layers and chemical-mechanical polishing (CMP) is presented. This method has allowed us to grow a relaxed graded buffer to 100% Ge without the increase in threading dislocation density normally observed in thick graded structures. This sample has been characterized by transmission electron microscopy, etch-pit density, atomic force microscopy, Nomarski optical microscopy, and triple-axis x-ray diffraction. Compared to other relaxed graded buffers in which CMP was not implemented, this sample exhibits improvements in threading dislocation density and surface roughness. We have also made process modifications in order to eliminate particles due to gas-phase nucleation and cracks due to thermal mismatch strain. We have achieved relaxed Ge on Si with a threading dislocation density of 2.1×106 cm−2, and we expect that further process refinements will lead to lower threading dislocation densities on the order of bulk Ge su...
620 citations
TL;DR: In this article, the opportunities and challenges of high-k/Ge MOSFETs are discussed on the basis of the material properties of Ge oxide to provide insights for future progress.
443 citations