Academic and industry research progress in germanium nanodevices
TL;DR: Germanium-based transistors have the potential to operate at high speeds with low power requirements and might therefore be used in non-silicon-based semiconductor technology in the future.
Abstract: Silicon has enabled the rise of the semiconductor electronics industry, but it was not the first material used in such devices. During the 1950s, just after the birth of the transistor, solid-state devices were almost exclusively manufactured from germanium. Today, one of the key ways to improve transistor performance is to increase charge-carrier mobility within the device channel. Motivated by this, the solid-state device research community is returning to investigating the high-mobility material germanium. Germanium-based transistors have the potential to operate at high speeds with low power requirements and might therefore be used in non-silicon-based semiconductor technology in the future.
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TL;DR: In this paper, a zinc-doped p-type epitaxial gallium-arsenide (epi-GaAs) film was grown on germanium (Ge) substrate at 675 °C by employing bi-layer of Al0.3Ga0.7As buffer along with 300 nm thick undoped GaAs.
1 citations
Dissertation•
01 May 2015
TL;DR: In this paper, the seed/catalyst-free growth of zinc oxide (ZnO) on single layer (SL) and multilayer (ML) graphene by thermal evaporation of Zn in the presence of oxygen (O2) gas was performed.
Abstract: Metal-oxide, namely zinc oxide (ZnO) nanostructures and thin films on graphene is interesting because these structures can offer additional functionality to graphene for realizing advanced electronic and optoelectronic applications. Graphene has a great potential for novel electronic devices because of its extraordinary electrical mobility exceeding 104 cm2/Vs and a thermal conductivity of 103 W/mK. Therefore, with the excellent electrical and thermal characteristics of graphene layers, the hybrid ZnO/graphene structure is expected to offer many sophisticated device applications such as sensing devices. In this study, the seed/catalyst-free growth of ZnO on single layer (SL) and multilayer (ML) graphene by thermal evaporation of Zn in the presence of oxygen (O2) gas was performed. The effects of substrate temperatures, substrate positions and graphene thicknesses on the morphological, structural, and optical properties were found to be very pronounced. The grown ZnO structures exhibit three different structures, i.e., nanoclusters, nanorods, and thin films at 600°C, 800°C, and 1,000°C, respectively. By setting the substrate to be inclined at 90°, the growth of ZnO nanostructures, namely nanoclusters and nanorods, on SL graphene was successfully realized at temperatures of 600°C and 800°C, respectively. However, no growth was achieved at 1,000°C due to the possible severe oxidation of graphene. For the growth on ML graphene at 600°C with an inclination angle of 90°, the grown structures show extremely thick and continuous cluster structures as compared to the growth with substrate’s inclination angle of 45°. Moreover, the base of nanorod structures grown at 800°C with an inclination angle of 90° also become thicker as compared to 45°, even though their densities and aspect ratios were almost unchanged. The morphologies of grown structures at 1,000°C with an inclination angle of 90° do not show significant difference with 45°. The intensity ratio of UV emission (IUV) and visible emission (IVIS) was changed, depending on the temperature. The structures grown at a low temperature of 600°C show the highest value of IUV/IVIS of 16.2, which is almost two times higher than the structures grown on SL graphene, indicating fewer structural defects. From the results obtained, the temperature below 800°C, substrate position inclined at 90° towards the gas flow, and ML graphene seems to be preferable parameters for the growth of ZnO structures by thermal evaporation because these factors can overcome the problem of graphene’s oxidation that takes place during the growth.
1 citations
Cites background from "Academic and industry research prog..."
...In recent years, a concept of the advanced heterogeneous integration of the Si platform has attracted much attention towards the recognition of a ‘More than Moore’ technology [1]....
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02 Jun 2014
TL;DR: In this paper, high tensile strained Ge(Sn) layers epitaxially grown on GeSn strain relaxed buffer layer have been presented, which mark a first step towards electronic device integration of low bandgap highly tensely strained group IV semiconductors.
Abstract: Highly tensile strained Ge(Sn) layers epitaxially grown on GeSn strain relaxed buffer layer have been presented. Electrical characterization exhibits good interfacial quality of the high-k gate stacks employing HfO2 on Ge and strained Ge. These results mark a first step towards electronic device integration of low bandgap highly tensely strained group IV semiconductors.
1 citations
TL;DR: In this article , the interaction of Ge(Si)/SOI self-assembled nanoislands with modes of photonic crystal slabs with a hexagonal lattice is studied in detail.
Abstract: The interaction of Ge(Si)/SOI self-assembled nanoislands with modes of photonic crystal slabs (PCS) with a hexagonal lattice is studied in detail. Appropriate selection of the PCS parameters and conditions for collecting the photoluminescence (PL) signal allowed to distinguish the PCS modes of different physical nature, particularly the radiative modes and modes associated to the bound states in the continuum (BIC). It is shown that the radiative modes with relatively low Q-factors could provide a increase greater than an order of magnitude in the integrated PL intensity in the wavelength range of 1.3–1.55 µm compared to the area outside of PCS at room temperature. At the same time, the interaction of Ge(Si) islands emission with the BIC-related modes provides the peak PL intensity increase of more than two orders of magnitude. The experimentally measured Q-factor of the PL line associated with the symmetry-protected BIC mode reaches the value of 2600.
1 citations
TL;DR: In this paper, high-resolution microscopies were used to study the interactions of Te atoms with Ge dislocation loops, after a standard n-type doping process in Ge.
Abstract: High resolution microscopies were used to study the interactions of Te atoms with Ge dislocation loops, after a standard n-type doping process in Ge. Te atoms neither segregate nor precipitate on dislocation loops, but form Te-Ge clusters at the same depth as dislocation loops, in contradiction with usual dopant behavior and thermodynamic expectations. Atomistic kinetic Monte Carlo simulations show that Te atoms are repulsed from dislocation loops due to elastic interactions, promoting homogeneous Te-Ge nucleation between dislocation loops. This phenomenon is enhanced by coulombic interactions between activated Te2+ or Te1+ ions.
1 citations
References
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01 Dec 2007
TL;DR: In this paper, a 45 nm logic technology is described that for the first time incorporates high-k + metal gate transistors in a high volume manufacturing process, resulting in the highest drive currents yet reported for NMOS and PMOS.
Abstract: A 45 nm logic technology is described that for the first time incorporates high-k + metal gate transistors in a high volume manufacturing process. The transistors feature 1.0 nm EOT high-k gate dielectric, dual band edge workfunction metal gates and third generation strained silicon, resulting in the highest drive currents yet reported for NMOS and PMOS. The technology also features trench contact based local routing, 9 layers of copper interconnect with low-k ILD, low cost 193 nm dry patterning, and 100% Pb-free packaging. Process yield, performance and reliability are demonstrated on 153 Mb SRAM arrays with SRAM cell size of 0.346 mum2, and on multiple microprocessors.
973 citations
08 Dec 2003
TL;DR: In this article, the authors describe a novel strained transistor architecture which is incorporated into a 90nm logic technology on 300mm wafers, which features an epitaxially grown strained SiGe film embedded in the source drain regions.
Abstract: This paper describes the details of a novel strained transistor architecture which is incorporated into a 90nm logic technology on 300mm wafers The unique strained PMOS transistor structure features an epitaxially grown strained SiGe film embedded in the source drain regions Dramatic performance enhancement relative to unstrained devices are reported These transistors have gate length of 45nm and 50nm for NMOS and PMOS respectively, 12nm physical gate oxide and Ni salicide World record PMOS drive currents of 700/spl mu/A//spl mu/m (high V/sub T/) and 800/spl mu/A//spl mu/m (low V/sub T/) at 12V are demonstrated NMOS devices exercise a highly tensile silicon nitride capping layer to induce tensile strain in the NMOS channel region High NMOS drive currents of 126mA//spl mu/m (high VT) and 145mA//spl mu/m (low VT) at 12V are reported The technology is mature and is being ramped into high volume manufacturing to fabricate next generation Pentium/spl reg/ and Intel/spl reg/ Centrino/spl trade/ processor families
729 citations
TL;DR: In this paper, a method of controlling threading dislocation densities in Ge on Si involving graded SiGe layers and chemical-mechanical polishing (CMP) is presented.
Abstract: A method of controlling threading dislocation densities in Ge on Si involving graded SiGe layers and chemical-mechanical polishing (CMP) is presented. This method has allowed us to grow a relaxed graded buffer to 100% Ge without the increase in threading dislocation density normally observed in thick graded structures. This sample has been characterized by transmission electron microscopy, etch-pit density, atomic force microscopy, Nomarski optical microscopy, and triple-axis x-ray diffraction. Compared to other relaxed graded buffers in which CMP was not implemented, this sample exhibits improvements in threading dislocation density and surface roughness. We have also made process modifications in order to eliminate particles due to gas-phase nucleation and cracks due to thermal mismatch strain. We have achieved relaxed Ge on Si with a threading dislocation density of 2.1×106 cm−2, and we expect that further process refinements will lead to lower threading dislocation densities on the order of bulk Ge su...
620 citations
TL;DR: In this article, the opportunities and challenges of high-k/Ge MOSFETs are discussed on the basis of the material properties of Ge oxide to provide insights for future progress.
443 citations