Academic and industry research progress in germanium nanodevices
TL;DR: Germanium-based transistors have the potential to operate at high speeds with low power requirements and might therefore be used in non-silicon-based semiconductor technology in the future.
Abstract: Silicon has enabled the rise of the semiconductor electronics industry, but it was not the first material used in such devices. During the 1950s, just after the birth of the transistor, solid-state devices were almost exclusively manufactured from germanium. Today, one of the key ways to improve transistor performance is to increase charge-carrier mobility within the device channel. Motivated by this, the solid-state device research community is returning to investigating the high-mobility material germanium. Germanium-based transistors have the potential to operate at high speeds with low power requirements and might therefore be used in non-silicon-based semiconductor technology in the future.
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TL;DR: In this article, a review of the high-K gate stack is presented, including the choice of oxides, their deposition, their structural and metallurgical behaviour, atomic diffusion, interface structure, their electronic structure, band offsets, electronic defects, charge trapping and conduction mechanisms, reliability, mobility degradation and oxygen scavenging.
Abstract: The scaling of complementary metal oxide semiconductor (CMOS) transistors has led to the silicon dioxide layer used as a gate dielectric becoming so thin that the gate leakage current becomes too large. This led to the replacement of SiO2 by a physically thicker layer of a higher dielectric constant or ‘high-K’ oxide such as hafnium oxide. Intensive research was carried out to develop these oxides into high quality electronic materials. In addition, the incorporation of Ge in the CMOS transistor structure has been employed to enable higher carrier mobility and performance. This review covers both scientific and technological issues related to the high-K gate stack – the choice of oxides, their deposition, their structural and metallurgical behaviour, atomic diffusion, interface structure, their electronic structure, band offsets, electronic defects, charge trapping and conduction mechanisms, reliability, mobility degradation and oxygen scavenging to achieve the thinnest oxide thicknesses. The high K oxides were implemented in conjunction with a replacement of polycrystalline Si gate electrodes with metal gates. The strong metallurgical interactions between the gate electrodes and the HfO2 which resulted an unstable gate threshold voltage resulted in the use of the lower temperature ‘gate last’ process flow, in addition to the standard ‘gate first’ approach. Work function control by metal gate electrodes and by oxide dipole layers is discussed. The problems associated with high K oxides on Ge channels are also discussed.
512 citations
01 Aug 2018
TL;DR: This Perspective argues that electronics is poised to enter a new era of scaling – hyper-scaling – driven by advances in beyond-Boltzmann transistors, embedded non-volatile memories, monolithic three-dimensional integration and heterogeneous integration techniques.
Abstract: In the past five decades, the semiconductor industry has gone through two distinct eras of scaling: the geometric (or classical) scaling era and the equivalent (or effective) scaling era. As transistor and memory features approach 10 nanometres, it is apparent that room for further scaling in the horizontal direction is running out. In addition, the rise of data abundant computing is exacerbating the interconnect bottleneck that exists in conventional computing architecture between the compute cores and the memory blocks. Here we argue that electronics is poised to enter a new, third era of scaling — hyper-scaling — in which resources are added when needed to meet the demands of data abundant workloads. This era will be driven by advances in beyond-Boltzmann transistors, embedded non-volatile memories, monolithic three-dimensional integration and heterogeneous integration techniques. This Perspective argues that electronics is poised to enter a new era of scaling – hyper-scaling – driven by advances in beyond-Boltzmann transistors, embedded non-volatile memories, monolithic three-dimensional integration, and heterogeneous integration techniques.
343 citations
TL;DR: A four-qubit quantum processor based on hole spins in germanium quantum dots is demonstrated and coherent evolution is obtained by incorporating dynamical decoupling, a step towards quantum error correction and quantum simulation using quantum dots.
Abstract: The prospect of building quantum circuits1,2 using advanced semiconductor manufacturing makes quantum dots an attractive platform for quantum information processing3,4. Extensive studies of various materials have led to demonstrations of two-qubit logic in gallium arsenide5, silicon6–12 and germanium13. However, interconnecting larger numbers of qubits in semiconductor devices has remained a challenge. Here we demonstrate a four-qubit quantum processor based on hole spins in germanium quantum dots. Furthermore, we define the quantum dots in a two-by-two array and obtain controllable coupling along both directions. Qubit logic is implemented all-electrically and the exchange interaction can be pulsed to freely program one-qubit, two-qubit, three-qubit and four-qubit operations, resulting in a compact and highly connected circuit. We execute a quantum logic circuit that generates a four-qubit Greenberger−Horne−Zeilinger state and we obtain coherent evolution by incorporating dynamical decoupling. These results are a step towards quantum error correction and quantum simulation using quantum dots. Using germanium quantum dots, a four-qubit processor capable of single-, two-, three-, and four-qubit gates, demonstrated by the creation of four-qubit Greenberger−Horne−Zeilinger states, is the largest yet realized with solid-state electron spins.
222 citations
TL;DR: The experimental results and DFT simulation results indicated that the tetragonal CsPb2Br5 is an indirect bandgap semiconductor that is PL-inactive with a bandgap of 2.979 eV.
201 citations
TL;DR: In this paper, the transition from an indirect to a fundamental direct bandgap material will be discussed, and the most commonly used approaches, i.e., molecular beam epitaxy (MBE) and chemical vapor deposition (CVD), will be reviewed in terms of crucial process parameters, structural as well as optical quality and employed precursor combinations including Germanium hydrides, Silicon hydride and a variety of Sn compounds like SnD4, SnCl4 or C6H5SnD3.
193 citations
References
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TL;DR: In this article, the effect of strain on hole transport in InGaAs/InP QW structures was analyzed at various temperatures (T = 77-300 K) using Hall measurements and the current best results include room temperature mobility and sheet resistance of 390 cm 2 /V-s and 8500 Ω/sq.
Abstract: We present experimental results on the effect of strain on hole transport in InGaAs quantum well (QW) structures. Indium content was varied from lattice matched to high compressive stress in InGaAs/InP QW and the transport properties were analyzed at various temperatures (T = 77-300 K) using Hall measurements. The effect of QW thickness (4-20 nm) on hole transport is also presented. The current best results include room temperature mobility and sheet resistance of 390 cm 2 /V-s and 8500 Ω/sq., respectively. It was observed that the mobility had a T -1.8 dependence indicating similar scattering mechanism in almost all of the samples with prominent mechanism being due to interface and barrier scattering. Further optimization of p-channel for InGaAs CMOS needs to be performed using the above results as guidelines.
7 citations
TL;DR: In this article, the authors studied channel width dependence of mobility in Ge channel modulation-doped structures fabricated by solid-source molecular beam epitaxy using the low-temperature buffer technique.
Abstract: We systematically studied channel width dependence of mobility in Ge channel modulation- doped structures fabricated by solid-source molecular beam epitaxy using the low-temperature buffer technique. This technique made it possible to obtain high-quality strain-relaxed Si1-xGex buffer layers having a very smooth surface (~5 nm). It was found that the mobility had a maximum around the channel width (Wch) of 7.5 nm and that it reached 13000 cm2/Vs at 20 K and 1175 cm2/Vs at room temperature (RT). The decrease in mobility with decreasing channel width was attributed to interface roughness scattering, since its influence increased as Wch decreased. On the other hand, the decrease in mobility for wider channels was considered to come from strain relaxation of Ge channel layers. In fact, high-resolution X-ray diffraction measurements revealed that strain relaxation of Ge channel layers occurred in the sample with Wch=20 nm. By lowering the growth temperature of Ge channel layers to suppress the strain relaxation, the mobility of 1320 cm2/Vs at RT was achieved.
6 citations
01 Jan 2000
TL;DR: In this paper, the authors reported a two dimensional hole gas system in pure germanium channels, where the hole mobility is limited by roughness scattering at the alloy-Ge interface at low temperatures and by parallel conduction at high temperatures.
Abstract: Recently there has been a lot of interest in two dimensional hole gas systems in pure germanium channels, since Ge has the highest intrinsic bulk hole mobility of all the commonly employed semiconductors, being comparable to the electron mobilites in bulk Si. Konig et. al. [l] have reported a maximum extrinsic transconductance of 125mS/mm(290mS/mm) at 300K(77K) in these Ge channel FETs. However, the hole mobility achieved in these systems are limited by roughness scattering at the alloy-Ge interface at low temperatures and by parallel conduction at high temperatures. Engelhardt et. al. [2] have reported a maximum hole mobility of $1300cm^2/Vs$ at room temperature with the channel density changing by about 50% from 4.2K to 300K, indicating the presence of parallel conduction.
1 citations