Academic and industry research progress in germanium nanodevices
TL;DR: Germanium-based transistors have the potential to operate at high speeds with low power requirements and might therefore be used in non-silicon-based semiconductor technology in the future.
Abstract: Silicon has enabled the rise of the semiconductor electronics industry, but it was not the first material used in such devices. During the 1950s, just after the birth of the transistor, solid-state devices were almost exclusively manufactured from germanium. Today, one of the key ways to improve transistor performance is to increase charge-carrier mobility within the device channel. Motivated by this, the solid-state device research community is returning to investigating the high-mobility material germanium. Germanium-based transistors have the potential to operate at high speeds with low power requirements and might therefore be used in non-silicon-based semiconductor technology in the future.
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TL;DR: In this article, a review of the high-K gate stack is presented, including the choice of oxides, their deposition, their structural and metallurgical behaviour, atomic diffusion, interface structure, their electronic structure, band offsets, electronic defects, charge trapping and conduction mechanisms, reliability, mobility degradation and oxygen scavenging.
Abstract: The scaling of complementary metal oxide semiconductor (CMOS) transistors has led to the silicon dioxide layer used as a gate dielectric becoming so thin that the gate leakage current becomes too large. This led to the replacement of SiO2 by a physically thicker layer of a higher dielectric constant or ‘high-K’ oxide such as hafnium oxide. Intensive research was carried out to develop these oxides into high quality electronic materials. In addition, the incorporation of Ge in the CMOS transistor structure has been employed to enable higher carrier mobility and performance. This review covers both scientific and technological issues related to the high-K gate stack – the choice of oxides, their deposition, their structural and metallurgical behaviour, atomic diffusion, interface structure, their electronic structure, band offsets, electronic defects, charge trapping and conduction mechanisms, reliability, mobility degradation and oxygen scavenging to achieve the thinnest oxide thicknesses. The high K oxides were implemented in conjunction with a replacement of polycrystalline Si gate electrodes with metal gates. The strong metallurgical interactions between the gate electrodes and the HfO2 which resulted an unstable gate threshold voltage resulted in the use of the lower temperature ‘gate last’ process flow, in addition to the standard ‘gate first’ approach. Work function control by metal gate electrodes and by oxide dipole layers is discussed. The problems associated with high K oxides on Ge channels are also discussed.
512 citations
01 Aug 2018
TL;DR: This Perspective argues that electronics is poised to enter a new era of scaling – hyper-scaling – driven by advances in beyond-Boltzmann transistors, embedded non-volatile memories, monolithic three-dimensional integration and heterogeneous integration techniques.
Abstract: In the past five decades, the semiconductor industry has gone through two distinct eras of scaling: the geometric (or classical) scaling era and the equivalent (or effective) scaling era. As transistor and memory features approach 10 nanometres, it is apparent that room for further scaling in the horizontal direction is running out. In addition, the rise of data abundant computing is exacerbating the interconnect bottleneck that exists in conventional computing architecture between the compute cores and the memory blocks. Here we argue that electronics is poised to enter a new, third era of scaling — hyper-scaling — in which resources are added when needed to meet the demands of data abundant workloads. This era will be driven by advances in beyond-Boltzmann transistors, embedded non-volatile memories, monolithic three-dimensional integration and heterogeneous integration techniques. This Perspective argues that electronics is poised to enter a new era of scaling – hyper-scaling – driven by advances in beyond-Boltzmann transistors, embedded non-volatile memories, monolithic three-dimensional integration, and heterogeneous integration techniques.
343 citations
TL;DR: A four-qubit quantum processor based on hole spins in germanium quantum dots is demonstrated and coherent evolution is obtained by incorporating dynamical decoupling, a step towards quantum error correction and quantum simulation using quantum dots.
Abstract: The prospect of building quantum circuits1,2 using advanced semiconductor manufacturing makes quantum dots an attractive platform for quantum information processing3,4. Extensive studies of various materials have led to demonstrations of two-qubit logic in gallium arsenide5, silicon6–12 and germanium13. However, interconnecting larger numbers of qubits in semiconductor devices has remained a challenge. Here we demonstrate a four-qubit quantum processor based on hole spins in germanium quantum dots. Furthermore, we define the quantum dots in a two-by-two array and obtain controllable coupling along both directions. Qubit logic is implemented all-electrically and the exchange interaction can be pulsed to freely program one-qubit, two-qubit, three-qubit and four-qubit operations, resulting in a compact and highly connected circuit. We execute a quantum logic circuit that generates a four-qubit Greenberger−Horne−Zeilinger state and we obtain coherent evolution by incorporating dynamical decoupling. These results are a step towards quantum error correction and quantum simulation using quantum dots. Using germanium quantum dots, a four-qubit processor capable of single-, two-, three-, and four-qubit gates, demonstrated by the creation of four-qubit Greenberger−Horne−Zeilinger states, is the largest yet realized with solid-state electron spins.
222 citations
TL;DR: The experimental results and DFT simulation results indicated that the tetragonal CsPb2Br5 is an indirect bandgap semiconductor that is PL-inactive with a bandgap of 2.979 eV.
201 citations
TL;DR: In this paper, the transition from an indirect to a fundamental direct bandgap material will be discussed, and the most commonly used approaches, i.e., molecular beam epitaxy (MBE) and chemical vapor deposition (CVD), will be reviewed in terms of crucial process parameters, structural as well as optical quality and employed precursor combinations including Germanium hydrides, Silicon hydride and a variety of Sn compounds like SnD4, SnCl4 or C6H5SnD3.
193 citations
References
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14 Jun 2005
TL;DR: In this article, the tradeoffs between higher mobility (smaller bandgap) channel and lower band-to-bandtunneling (BTBT) leakage have been investigated through detailed experiments and simulations.
Abstract: For the first time, the tradeoffs between higher mobility (smaller bandgap) channel and lower band-to-band-tunneling (BTBT) leakage have been investigated through detailed experiments and simulations. The resulting optimal structure obtained was an ultra-thin, low defect, 2nm fully strained Ge epi channel on relaxed Si, with a 4nm Si cap layer. The fabricated device shows very high mobility enhancements >3.5X over bulk Si devices, 2X mobility enhancement and >10X BTBT reduction over 4nm strained Ge and surface channel 50% strained SiGe devices.
38 citations
TL;DR: In this paper, the hole mobility characteristics of 〈110〉 /(100)-oriented asymmetrically strained-SiGe p-MOSFETs are studied.
Abstract: The hole mobility characteristics of 〈110〉 /(100)-oriented asymmetrically strained-SiGe p-MOSFETs are studied. Uniaxial mechanical strain is applied to biaxial compressive strained devices and the relative change in effective hole mobility is measured. The channel Ge content varies from 0 to 100%. Up to -2.6% biaxial compressive strain is present in the channel and an additive uniaxial strain component of -0.06% is applied via mechanical bending. The hole mobility in biaxial compressive strained-SiGe is enhanced relative to relaxed Si. It is observed that this mobility enhancement increases further with the application of 〈110〉 longitudinal uniaxial compressive strain. The relative change in mobility with applied stress is larger for biaxial compressive strained-SiGe than for Si and increases with the amount of biaxial compressive strain present in the channel.
38 citations
05 Dec 2005
TL;DR: In this paper, the same process for a dual channel integration scheme was used to achieve symmetric n-and p-MOSFET IDsat performance with high-k gate dielectric.
Abstract: Epitaxial strained Si and Ge n- and p-MOSFETs with a TiN/HfO2 gate stack were fabricated with the same process for a dual channel integration scheme Compared to the HfO2/Si reference, X17 strained Si electron and X9 strained Ge hole mobility gains are demonstrated, achieving symmetric n- and p-MOSFET IDsat performance This X9 strained Ge hole mobility enhancement highly exceeds previous reported results on Ge pMOSFETs with high-k dielectrics For the first time, such a hole mobility enhancement, theoretically predicted and experimentally reported with thick SiO2 gate dielectrics, is demonstrated with a thin high-k gate dielectric (EOT=14Aring)
38 citations
TL;DR: In this paper, the authors demonstrate the selective growth of high quality Ge epitaxial layers in channels as narrow as 10 nm on patterned Si (001) substrates by a combination of low temperature growth and selective recrystallization using Ge melt and regrowth during a millisecond laser anneal.
Abstract: We demonstrate the selective growth of high quality Ge epitaxial layers in channels as narrow as 10 nm on patterned Si (001) substrates by a combination of low temperature growth and selective recrystallization using Ge melt and regrowth during a millisecond laser anneal. Filling narrow trenches at high growth temperature as required for obtaining high quality layers was shown to be prohibited by Ge outdiffusion due to the high Ge chemical potential in such narrow channels. At low temperature, a hydride-terminated surface is maintained which counteracts the outdiffusion of the Ge adatoms and provides excellent trench filling. The resulting low crystalline quality can be restored by a selective Ge melt and epitaxial regrowth using a millisecond laser anneal.
36 citations
01 Dec 2006
TL;DR: In this paper, the impact of lateral and vertical scaling of In0.7Ga0.3As HEMTs on their logic performance was investigated, and it was shown that reducing the thickness of the insulator results in better electrostatic integrity and improved short-channel effects.
Abstract: We have experimentally investigated the impact of lateral and vertical scaling of In0.7Ga0.3As HEMTs on their logic performance. Reducing the In0.52Al0.48As insulator thickness results in much better electrostatic integrity and improved short-channel effects down to a gate length of 60 nm. Our nearly enhancement-mode 60 nm HEMTs feature VT = -0.02 V, DIBL = 93 mV/V and S = 88 mV/V. For a given value of ION/I OFF = 103, we obtain CV/I = 0.85 ps at Vcc = 0.5 V. For the same leakage current, these devices exhibit 2.5 times more current drive than state-of-the-art low-power 65 nm CMOS
34 citations