Academic and industry research progress in germanium nanodevices
TL;DR: Germanium-based transistors have the potential to operate at high speeds with low power requirements and might therefore be used in non-silicon-based semiconductor technology in the future.
Abstract: Silicon has enabled the rise of the semiconductor electronics industry, but it was not the first material used in such devices. During the 1950s, just after the birth of the transistor, solid-state devices were almost exclusively manufactured from germanium. Today, one of the key ways to improve transistor performance is to increase charge-carrier mobility within the device channel. Motivated by this, the solid-state device research community is returning to investigating the high-mobility material germanium. Germanium-based transistors have the potential to operate at high speeds with low power requirements and might therefore be used in non-silicon-based semiconductor technology in the future.
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TL;DR: In this article, a review of the high-K gate stack is presented, including the choice of oxides, their deposition, their structural and metallurgical behaviour, atomic diffusion, interface structure, their electronic structure, band offsets, electronic defects, charge trapping and conduction mechanisms, reliability, mobility degradation and oxygen scavenging.
Abstract: The scaling of complementary metal oxide semiconductor (CMOS) transistors has led to the silicon dioxide layer used as a gate dielectric becoming so thin that the gate leakage current becomes too large. This led to the replacement of SiO2 by a physically thicker layer of a higher dielectric constant or ‘high-K’ oxide such as hafnium oxide. Intensive research was carried out to develop these oxides into high quality electronic materials. In addition, the incorporation of Ge in the CMOS transistor structure has been employed to enable higher carrier mobility and performance. This review covers both scientific and technological issues related to the high-K gate stack – the choice of oxides, their deposition, their structural and metallurgical behaviour, atomic diffusion, interface structure, their electronic structure, band offsets, electronic defects, charge trapping and conduction mechanisms, reliability, mobility degradation and oxygen scavenging to achieve the thinnest oxide thicknesses. The high K oxides were implemented in conjunction with a replacement of polycrystalline Si gate electrodes with metal gates. The strong metallurgical interactions between the gate electrodes and the HfO2 which resulted an unstable gate threshold voltage resulted in the use of the lower temperature ‘gate last’ process flow, in addition to the standard ‘gate first’ approach. Work function control by metal gate electrodes and by oxide dipole layers is discussed. The problems associated with high K oxides on Ge channels are also discussed.
512 citations
01 Aug 2018
TL;DR: This Perspective argues that electronics is poised to enter a new era of scaling – hyper-scaling – driven by advances in beyond-Boltzmann transistors, embedded non-volatile memories, monolithic three-dimensional integration and heterogeneous integration techniques.
Abstract: In the past five decades, the semiconductor industry has gone through two distinct eras of scaling: the geometric (or classical) scaling era and the equivalent (or effective) scaling era. As transistor and memory features approach 10 nanometres, it is apparent that room for further scaling in the horizontal direction is running out. In addition, the rise of data abundant computing is exacerbating the interconnect bottleneck that exists in conventional computing architecture between the compute cores and the memory blocks. Here we argue that electronics is poised to enter a new, third era of scaling — hyper-scaling — in which resources are added when needed to meet the demands of data abundant workloads. This era will be driven by advances in beyond-Boltzmann transistors, embedded non-volatile memories, monolithic three-dimensional integration and heterogeneous integration techniques. This Perspective argues that electronics is poised to enter a new era of scaling – hyper-scaling – driven by advances in beyond-Boltzmann transistors, embedded non-volatile memories, monolithic three-dimensional integration, and heterogeneous integration techniques.
343 citations
TL;DR: A four-qubit quantum processor based on hole spins in germanium quantum dots is demonstrated and coherent evolution is obtained by incorporating dynamical decoupling, a step towards quantum error correction and quantum simulation using quantum dots.
Abstract: The prospect of building quantum circuits1,2 using advanced semiconductor manufacturing makes quantum dots an attractive platform for quantum information processing3,4. Extensive studies of various materials have led to demonstrations of two-qubit logic in gallium arsenide5, silicon6–12 and germanium13. However, interconnecting larger numbers of qubits in semiconductor devices has remained a challenge. Here we demonstrate a four-qubit quantum processor based on hole spins in germanium quantum dots. Furthermore, we define the quantum dots in a two-by-two array and obtain controllable coupling along both directions. Qubit logic is implemented all-electrically and the exchange interaction can be pulsed to freely program one-qubit, two-qubit, three-qubit and four-qubit operations, resulting in a compact and highly connected circuit. We execute a quantum logic circuit that generates a four-qubit Greenberger−Horne−Zeilinger state and we obtain coherent evolution by incorporating dynamical decoupling. These results are a step towards quantum error correction and quantum simulation using quantum dots. Using germanium quantum dots, a four-qubit processor capable of single-, two-, three-, and four-qubit gates, demonstrated by the creation of four-qubit Greenberger−Horne−Zeilinger states, is the largest yet realized with solid-state electron spins.
222 citations
TL;DR: The experimental results and DFT simulation results indicated that the tetragonal CsPb2Br5 is an indirect bandgap semiconductor that is PL-inactive with a bandgap of 2.979 eV.
201 citations
TL;DR: In this paper, the transition from an indirect to a fundamental direct bandgap material will be discussed, and the most commonly used approaches, i.e., molecular beam epitaxy (MBE) and chemical vapor deposition (CVD), will be reviewed in terms of crucial process parameters, structural as well as optical quality and employed precursor combinations including Germanium hydrides, Silicon hydride and a variety of Sn compounds like SnD4, SnCl4 or C6H5SnD3.
193 citations
References
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01 Mar 1991
TL;DR: Semiconductor Devices: Pioneering Papers as discussed by the authors is a collection of 141 pioneering papers on semiconductor devices covering a period of 100 years, from the earliest systematic investigation of metal-semiconductor contacts in 1874 to the first observation of the resonant tunneling in 1974.
Abstract: Semiconductor Devices: Pioneering Papers makes available an important collection of 141 pioneering papers on semiconductor devices covering a period of 100 years, from the earliest systematic investigation of metal-semiconductor contacts in 1874 to the first observation of the resonant tunneling in 1974. The first papers on all of the major semiconductor devices including the p - n junction, the heterojunction, the bipolar transistor, hot electron transistors, thyristors, the Schottky barrier, the Mott barrier, the JFET, the MESFET, the MOS diode, the charge-coupled device, the MOSFET, the CMOS, the nonvolatile memory, the tunnel diode, the quantum well, superlattice structures, the IMPATT diode, the BARITT diode, the transferred-electron device, the LED, the laser diode, the photodetector and the solar cell are included. Also presented are the classic papers on device physics and characterization such as the generation-recombination theory, the high injection theory, the avalanche breakdown theory, the Fowler-Nordheim tunneling theory, the noise theory, the Debye length concept, the Hall effect, the Early voltage, the Ebers-Moll model, the differential capacitance method, and the lifetime measurement technique.The papers are divided into four parts: bipolar, unipolar, special microwave, and photonic devices, with a commentary for each part to highlight the importance of each of the collected papers. This book serves as a useful reference for a first-hand look at the operational principles of devices as conceived by their inventors and to understand the basic device physics as documented by their discoverers.
33 citations
TL;DR: In this paper, high mobility two-dimensional hole gases have been achieved in p-type modulation doped Ge/SiGe heterostructures grown by MBE on a relaxed graded SiGe buffer.
Abstract: High mobility two-dimensional hole gases have been achieved in p -type modulation doped Ge/SiGe heterostructures grown by MBE on a relaxed graded SiGe buffer. Hall mobilities of up to 15,500 cm 2 /Vs at carrier densities of 1.04 × 10 12 cm −2 are observed at 0.4 K in magnetotransport. The cyclotron resonance (CR) shows a narrow (FWHM 15 cm −1 ) and strong absorption of up to 15%. Quantum transitions are resolved. A splitting of the CR is observed, attributed to the lifting of the spin degeneracy of the ±3/2 states at B = 0 due to the asymmetric confinement potential. Mean CR masses of 0.14 m 0 up to 0.20 m 0 are found depending on well width and carrier density.
33 citations
TL;DR: In this article, the electrical properties of n-Ge metal-oxide-semiconductor (MOS) capacitors with HfO2/LaON interlayer were investigated, and it was found that better electrical performances, including lower interface-state density, smaller gate leakage current, smaller capacitance equivalent thickness, larger k value, and negligible C-V frequency dispersion, can be achieved for the MOS device with LaON inter layer.
Abstract: The electrical properties of n-Ge metal-oxide-semiconductor (MOS) capacitors with HfO2/LaON or HfO2/La2O3 stacked gate dielectric (LaON or La2O3 as interlayer) are investigated. It is found that better electrical performances, including lower interface-state density, smaller gate leakage current, smaller capacitance equivalent thickness, larger k value, and negligible C-V frequency dispersion, can be achieved for the MOS device with LaON interlayer. The involved mechanism lies in that the LaON interlayer can effectively block the interdiffusions of Ge, O, and Hf, thus suppressing the growth of unstable GeOx interlayer and improving the dielectric/Ge interface quality.
29 citations
TL;DR: In this paper, the authors studied channel width dependence of mobility in Ge channel modulation-doped structures fabricated by solid-source molecular beam epitaxy using the low-temperature buffer technique.
Abstract: We systematically studied channel width dependence of mobility in Ge channel modulation- doped structures fabricated by solid-source molecular beam epitaxy using the low-temperature buffer technique. This technique made it possible to obtain high-quality strain-relaxed Si1-xGex buffer layers having a very smooth surface (~5 nm). It was found that the mobility had a maximum around the channel width (Wch) of 7.5 nm and that it reached 13000 cm2/Vs at 20 K and 1175 cm2/Vs at room temperature (RT). The decrease in mobility with decreasing channel width was attributed to interface roughness scattering, since its influence increased as Wch decreased. On the other hand, the decrease in mobility for wider channels was considered to come from strain relaxation of Ge channel layers. In fact, high-resolution X-ray diffraction measurements revealed that strain relaxation of Ge channel layers occurred in the sample with Wch=20 nm. By lowering the growth temperature of Ge channel layers to suppress the strain relaxation, the mobility of 1320 cm2/Vs at RT was achieved.
29 citations
TL;DR: In this article, the fabrication of Ge virtual substrates with low threading dislocation densities by selective growth and high temperature anneal followed by chemical mechanical polishing (CMP) was studied.
26 citations