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Journal ArticleDOI

Accurate and Computationally Efficient Modeling of Nonquasi Static Effects in MOSFETs for Millimeter-Wave Applications

01 Jan 2019-IEEE Transactions on Electron Devices (IEEE)-Vol. 66, Iss: 1, pp 44-51

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Citations
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TL;DR: In this article, a BSIM-based compact model for a high-voltage MOSFET is presented, which has been extended to include the overlap capacitance due to the drift region as well as quasi-saturation effect.
Abstract: A BSIM-based compact model for a high-voltage MOSFET is presented. The model uses the BSIM-BULK (formerly BSIM6) model at its core, which has been extended to include the overlap capacitance due to the drift region as well as quasi-saturation effect. The model is symmetric and continuous, is validated with the TCAD simulations and experimental 35- and 90-V LDMOS and 40-V VDMOS transistors, and shows excellent agreement.

5 citations

Journal ArticleDOI

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TL;DR: An improved model of bulk charge effect for both drain current and capacitances and its implementation in the industry standard Berkeley short-channel IGFET model (BSIM)-BULK model is presented.
Abstract: In this brief, we present an improved model of bulk charge effect for both drain current ( ${I}_{\text {DS}}$ ) and capacitances and its implementation in the industry standard Berkeley short-channel IGFET model (BSIM)-BULK model. The proposed model captures all the well-known and important bulk charge effects, as the Abulk term does for BSIM3/BSIM4. The model is validated with the experimental and technology computer-aided design (TCAD) data. The proposed model enhances the fitting accuracy for ${I}_{\text {DS}}$ , and more importantly its derivatives and capacitances too.

5 citations


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Proceedings ArticleDOI

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01 Apr 2019
TL;DR: The recent and upcoming enhancements of the industry standard BSIM-BULK model are presented and an analytical model for bulk charge effect, in both current and capacitance, is implemented to improve the model accuracy for transconductance and output conductance.
Abstract: In this work, we present the recent and upcoming enhancements of the industry standard BSIM-BULK (formerly BSIM6) model. BSIM-BULK is the latest body referenced compact model for bulk MOSFETs having a unified core, which is developed by the BSIM group for accurate design of analog and RF circuits. The model satisfies the symmetry test for DC and AC, correctly predicts harmonic slope, and exhibits accurate results for RF and analog simulations. In order to further improve the model accuracy for transconductance $(g_{m})$ and output conductance $(g_{ds})$, an analytical model for bulk charge effect, in both current and capacitance, is implemented. Several other advanced models are added to capture real device physics. These include: parasitic current at the shallow trench isolation edges; leakage current components in zero threshold voltage native devices; new model for NQS to capture the NQS effects up to the millimeter wave regime; self heating effect; and heavily halo implanted MOSFET’s anomalous g m , flicker noise and I DS mismatch. All these enhancements have been implemented to high standards of computational efficiency and robustness.

4 citations


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Proceedings ArticleDOI

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01 Sep 2019
TL;DR: Highlights from Silicon Device Physics, material sciences and electrical engineering are among the first results to be presented from GFs subcontracts in the IPCEI-project, namely a reconfigurable FET compatible with 22-FDX-technology, a CMOS compatible new material Si doped HfO2 for electrocaloric/ pyroelectric effects on chip.
Abstract: Highlights from Silicon Device Physics, material sciences and electrical engineering are among the first results to be presented from GFs subcontracts in the IPCEI-project, namely a reconfigurable FET compatible with 22-FDX-technology, a CMOS compatible new material Si doped HfO 2 for electrocaloric/ pyroelectric effects on chip, modelling of the 22FDX devices in the higher GHz range and first 5G Dual Band transceiver blocks designed in 22FDX

2 citations


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29 Jan 2021
TL;DR: In this paper, a fast optimization hyperparameter and sparse support vector machine (FOH-SSVM) algorithm was proposed to solve the problem of signal integrity, which greatly reduced the modeling time and increased the prediction accuracy.
Abstract: Compared with the traditional support vector machine regression (SVR), the SVR hyperparameter fast optimization algorithm can improve the accuracy of the prediction results. However, the data shows that when the training sample is too large, it will increase the complexity of model learning, resulting in too long modeling time. Therefore, we refer to the most effective support vector set search method in the variable selection and sparse support vector machine (VSߝSSVM) algorithm, and appropriately fit the “advantages” of these two algorithms to construct a fast optimization hyperparameter and sparse support vector machine (FOH-SSVM) algorithm. In this work, we use the algorithm to solve the problem of signal integrity. The experimental results show that the modeling time required by the FOH-SSVM algorithm is 1%, which greatly reduces the modeling time. At the same time, the prediction accuracy of the algorithm is increased by 8%, ensuring good prediction performance.

References
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01 Jan 1987
TL;DR: In this article, the MOS transistors with ION-IMPLANTED CHANNELS were used for CIRCUIT SIMULATION in a two-and three-tier MOS structure.
Abstract: 1. SEMICONDUCTORS, JUNCTIONS AND MOFSET OVERVIEW 2. THE TWO-TERMINAL MOS STRUCTURE 3. THE THREE-TERMINAL MOS STRUCTURE 4. THE FOUR-TERMINAL MOS STRUCTURE 5. MOS TRANSISTORS WITH ION-IMPLANTED CHANNELS 6. SMALL-DIMENSION EFFECTS 7. THE MOS TRANSISTOR IN DYNAMIC OPERATION - LARGE-SIGNAL MODELING 8. SMALL-SIGNAL MODELING FOR LOW AND MEDIUM FREQUENCIES 9. HIGH-FREQUENCY SMALL-SIGNAL MODELS 10.MOFSET MODELING FOR CIRCUIT SIMULATION

3,086 citations


"Accurate and Computationally Effici..." refers background in this paper

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Proceedings ArticleDOI

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01 Dec 1998
TL;DR: In this paper, a physics-based effective gate resistance model representing the non-quasi-static (NQS) effect and the distributed gate electrode resistance is proposed for accurately predicting the RF performance of CMOS devices.
Abstract: A physics-based effective gate resistance model representing the non-quasi-static (NQS) effect and the distributed gate electrode resistance is proposed for accurately predicting the RF performance of CMOS devices. The accuracy of the model is validated with 2D simulations and experimental data. In addition, the effect of the gate resistance on the device noise behavior has been studied with measured data. The result shows that an accurate gate resistance model is essential for the noise modeling.

171 citations


"Accurate and Computationally Effici..." refers background in this paper

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Journal ArticleDOI

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TL;DR: In this article, a non-quasi-static (NQS) MOSFET model is proposed for both large-signal transient and small-Signal ac analysis, which employs a physical relaxation time approach to take care of the finite channel charging time.
Abstract: A new non-quasi-static (NQS) MOSFET model, which is applicable for both large-signal transient and small-signal ac analysis, has been developed. It employs a physical relaxation time approach to take care of the finite channel charging time to reach equilibrium and the effect of instantaneous channel charge re-distribution. The NQS model is formulated independently from the dc I-V and the charge-capacitor model, thus can be easily applied to any existing simulators. The model has been implemented in the newly released BSIM3 version 3, and comparison has been made among this model, common quasi-static (QS) SPICE models and PISCES two-dimensional (2-D) numerical device simulator. While predicting accurate NQS behavior, the time penalty for using the new model is only about 20-30% more than the common QS models. It is much less than the time required by other NQS models reported. Limitations and compromises between simplicity, efficiency and accuracy are also discussed.

113 citations


"Accurate and Computationally Effici..." refers background in this paper

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TL;DR: In this article, a four-terminal small-signal dc-to-high-frequency model, valid in weak, moderate, and strong inversion regimes, for the intrinsic part of the long-channel MOS transistor is presented.
Abstract: This paper presents a four-terminal small-signal dc-to-high-frequency model, valid in weak, moderate, and strong inversion regimes, for the intrinsic part of the long-channel MOS transistor. A charge-sheet approximation is used. Basic MOSFET equations are separated into parts corresponding to dc and ac small-signal components. The former are used to evaluate the drain current under dc conditions; the latter, describing the "transmission-line" behavior of the MOSFET, are solved to arrive at a complete set of admittance parameters. Based on different approximations of these parameters, various models are presented, each of different upper frequency limit of validity. For each model parameter, a single continuous expression is used which is valid in all regions of operation (weak inversion, moderate inversion, strong inversion; nonsaturation and saturation). The frequency range of validity of these models and the inadequacies of the quasistatic models at high frequencies are discussed. It is shown that at low frequencies the high-frequency model reduces to a quasistatic model which is widely verified by experimental results; at high frequencies the model agrees with available measurements.

111 citations


"Accurate and Computationally Effici..." refers background in this paper

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TL;DR: In this paper, a field-effect transistor of planar geometry is considered as an active, distributed, nonuniform transmission line and the wave equation of this line is determined and solved by an approximation method.
Abstract: In this theory a field-effect transistor of planar geometry is considered as an active, distributed, nonuniform transmission line. The wave equation of this line is determined and solved by an approximation method. From this solution the y parameters are determined. By comparing the results for y 11 with van der Ziel's expression for the high-frequency gate noise of field-effect transistors, it is shown that the noise temperature of y 11 is of the order of the device temperature. The conductance part g 11 of y 11 varies as ω2over a wide frequency range. The high-frequency cutoff of the field-effect transistor is determined.

81 citations


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