Proceedings ArticleDOI
Achieving sub-adiabatic energy dissipation by varying V BS
Prasad D. Khandekar,Shaila Subbaraman +1 more
- Vol. 01, pp 600-603
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TLDR
In this article, the authors proposed a new method of reducing the energy dissipation below that of quasi-adiabatic circuit, which is proving to be an attractive solution for low power digital design.Abstract:
This paper proposes a new method of reducing the energy dissipation below that of quasi-adiabatic circuit. Adiabatic logic style is proving to be an attractive solution for low power digital design. Many researchers have introduced different adiabatic logic styles in last few years and proved that these are better than CMOS as far as power dissipation is concerned. In this paper, we present control circuits for sub-adiabatic energy dissipation and show that the energy dissipation of the quasi-adiabatic circuit can be further reduced if we control bulk-to-source voltage, V BS appropriately. All the inverter circuits are designed using 180nm technology in Cadence design environment.read more
Citations
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Proceedings ArticleDOI
Implementation and analysis of VCO based power-clock supply generator
TL;DR: The design and simulation results of a VCO based power-clock supply generation for quasi-adiabatic circuits using 180nm technology using cell based design approach are discussed.
References
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Journal ArticleDOI
Low-power digital systems based on adiabatic-switching principles
TL;DR: The dissipation of the adiabatic amplifier is compared to that of conventional switching circuits, both for the case of a fixed voltage swing and the case when the voltage swing can be scaled to reduce power dissipation.
Journal ArticleDOI
An efficient charge recovery logic circuit
Yong Moon,Deog-Kyoon Jeong +1 more
TL;DR: Efficient charge recovery logic (ECRL) is proposed as a candidate for low-energy adiabatic logic circuit and shows four to six times power reduction with a practical loading and operation frequency range.
Journal ArticleDOI
Pass-transistor adiabatic logic using single power-clock supply
TL;DR: In this article, a pass-transistor adiabatic logic (PAL) was proposed to operate from a single power-clock supply and outperforms the previously reported adiabilistic logic techniques in terms of its energy use.
Journal ArticleDOI
Clocked CMOS adiabatic logic with integrated single-phase power-clock supply
TL;DR: CAL is a dual-rail logic that operates from a single-phase AC power-clock supply that makes it possible to integrate all power control circuitry on the chip, resulting in better system efficiency, lower cost, and simpler power distribution.
Journal ArticleDOI
Switched-source-impedance CMOS circuit for low standby subthreshold current giga-scale LSI's
TL;DR: In this paper, a switched-source-impedance (SSI) CMOS circuit is proposed as a means of reducing the exponential increase of sub-threshold current with threshold-voltage scaling.