Active bank switching for temperature control of the register file in a microprocessor
TL;DR: Experimental results show that this periodic active bank switching scheme achieves 3.4°C of steady-state temperature reduction, with a mere 0.75% average performance penalty.
Abstract: An effective thermal management scheme, called active bank switching, for temperature control in the register file of a microprocessor is presented. The idea is to divide the physical register file into two equal-sized banks, and to alternate between the two banks when allocating new registers to the instruction operands. Experimental results show that this periodic active bank switching scheme achieves 3.4°C of steady-state temperature reduction, with a mere 0.75% average performance penalty.
Summary (3 min read)
- Peak power dissipation and the resulting temperature rise have become a limiting factor to microprocessor performance and a significant component of its cost.
- Dynamic thermal management (DTM) has been proposed as a class of microarchitectural solutions and software strategies to achieve the highest processor performance under a peak temperature limit.
- A DTM method specifically targeted toward temperature control in the register file was presented in .
- This method, called activity migration, is quite effective, albeit it has a large area overhead.
- The authors idea is based on the observation that the register file is not fully utilized over a program’s execution, i.e., the lifetime of registers/operands are short such that the authors only need a rather small number of physical registers to be active during most of the cpu cycles.
2.1 Register File Utilization
- Many 32-bit instruction set architectures (ISA) are designed to have 32 architectural registers although modern superscalar processors have more than 32 physical registers.
- Note that on average for about 90% the time, less than a half of the physical registers (32) are actually allocated.
- This is because although a new instruction is dispatched and allocated to a physical register, much of the time this instruction is not issued and executed due to the data dependencies among instructions.
2.2 Periodic Bank Switching: The Idea
- Based on the above observation, the authors propose to divide the register file into two equal-sized banks and use only one bank at a time, i.e., the number of physical registers available at any time is one half of the original count and registers are allocated from one of these two banks.
- Here the authors designate the active bank as a primary bank and the other one as a secondary bank.
- Registers are allocated first from the primary bank and only if the primary bank is full, the allocation is done from the secondary bank.
- When bank switching occurs, there might still be some references to the nonactive bank.
- These pending references will be relatively small compared to the number of references to the active bank.
2.3 Thermal Zones and Thermal Gradients
- The authors have carried out detailed analysis of the temperature regions in terms of thermal gradients and classified them into two zones: 1) Fast Temperature Rise (FTR) zone:.
- The rising thermal gradient is higher than the falling thermal gradient i.e., the temperature rises faster than it falls (when the chip is allowed to cool off).
- Based on their simulations , the FTF zone is above the FTR zone.
- This is fortunate because the temperature profile of a microprocessor chip is such that DTM techniques become more effective as the chip temperature rises.
- If the ST lies in the FTF zone, then the DTM methods tend to work very well and the new ST of the chip will be significantly lower.
2.4 Thermal Model
- To mathematically support the periodic active bank switching idea, the authors use a thermal model developed by Skadron et al. in .
- After a time interval, the new temperature becomes: new oldT T T= + Δ (2) Let tinitial and tfinal denote two instances of time (and their difference be denoted by ∆t), respectively.
- More precisely, a simple DTM policy where the authors regularly (i.e., at fixed timing intervals) switch between the primary and secondary banks is sufficient.
- The authors have found that a fixed interval of 10M CPU cycles is adequate for their purposes and that the overall reduction in ST is not sensitive to the exact length of this interval.
- Similarly, the actual rising thermal gradient in the newly active bank is smaller than equation (3) since some of the registers previously mapped to the sleep bank are alive and accessed from that bank for certain cycles.
- It is expected that the banked structure in physical register file needs extra control logics and the renaming logic need to be changed to allocate new registers from the active bank only.
- These area penalties are much smaller than those for the activity migration method, which duplicates the entire register file.
- Furthermore, the periodic active bank switching scheme does not have self-producing performance penalty as is the case for the activity migration method since the authors do not need to transfer the content of registers from one bank to the other.
- For the experiments, the authors integrate SimpleScalar , Wattch  and Hotspot  into one simulator.
- The authors position this half sized register file in the center of the register file area and the surrounding area is kept empty ).
- For the first 200K cycles of each benchmark program run, the authors obtain the typical power figure for the register file (along with other functional units).
- The thermal simulation is carried out in order to find the steady-state temperature for the register file.
- For the test applications, the authors used SPEC2000INT benchmarks  with reference/train input files, Mediabench program  and MPEG-2 decoder program .
3.3 Experimental Results
- Next, the authors ran the application with a banked register file with active bank switching.
- Note the relationship between the steady-state temperature and the IPC of each program: Compared to the upper curve, note that (a) the application program’s thermal behavior is maintained in the lower curves, and (b) the periodic active bank switching is observed between the two lower curves.
- Note also that two lower curves lay one upon another with very small thermal differences.
- The performance penalties reported correspond half sized (32) register file.
- The authors presented an effective steady-state temperature reduction method by adopting a banked structure in the register file.
- In their scheme, only one bank is active at a time and the authors keep switching between the two available banks.
- With banking, the authors achieve a sizeable steady-state temperature reduction with a small performance penalty.
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An effective thermal management scheme, called active bank switching, for temperature control in the register file of a microprocessor is presented.