Proceedings ArticleDOI
Adaptive Low Power RTPG for BIST based test applications
Renju Thomas John,K D Sreekanth,S. Sivanantham +2 more
- pp 933-936
Reads0
Chats0
TLDR
A Low Power Random Test Pattern Generator (LPRTPG) is presenting to improve the tradeoff between shift power reduction and the test coverage loss and to get the required tradeoff, an adaptive type technique is utilizing.Abstract:
Power reduction during testing is an important concern in scan based tests. But methods to reduce shift power will results in test coverage loss. So a Low Power Random Test Pattern Generator (LPRTPG) is presenting to improve the tradeoff between shift power reduction and the test coverage loss. To get the required tradeoff, an adaptive type technique is utilizing where the previous test responses are given as feedback to a transition controller which is capable of generating highly correlated test patterns. The experimental results on ISCAS'89 benchmark circuits' shows efficiency of the work in terms of reduction in test power.read more
Citations
More filters
Journal Article
Built-in Self-Test Methodology for System-on-a-Chip Testing
S. Sivanantham,T Tresa +1 more
TL;DR: A test pattern generation methodology for detection of transition faults using in-circuit arithmetic circuits for reduced area overhead and the power of the test pattern generator is presented.
Journal ArticleDOI
Choice of granularity for reliable circuit design using dynamic reconfiguration
TL;DR: Optimum granule-sizes in designing various fault tolerant circuits from ripple carry adder to CORDIC as well as Viterbi decoder have been derived.
Journal Article
Testing Technique of BIST: A Survey
TL;DR: This survey paper focus on “Chip” Built in Self-Test (BIST) study and its promotion for board and system-level applications and its testing techniques.
Journal ArticleDOI
Built in Self Test Architecture Using Logic Module
TL;DR: A Built-in self-test technique that provides the capability of performing at speed testing with high fault coverage, whereas at the same time they relax the reliance on expensive external testing equipment is constituted a striking solution to the problem of testing VLSI devices.
Patent
Reducing power requirements and switching during logic built-in-self-test and scan test
TL;DR: In this paper, the flip-flops are scanned-out from the flipflops and a prediction is made of a number of switching transitions between a current capture clock cycle and a next one.
References
More filters
Proceedings ArticleDOI
Combinational profiles of sequential benchmark circuits
F. Brglez,D. Bryan,K. Kozminski +2 more
TL;DR: A set of 31 digital sequential circuits described at the gate level that extend the size and complexity of the ISCAS'85 set of combinational circuits and can serve as benchmarks for researchers interested in sequential test generation, scan-basedtest generation, and mixed sequential/scan-based test generation using partial scan techniques.
Book
Essentials of Electronic Testing for Digital, Memory and Mixed-Signal VLSI Circuits
TL;DR: This book provides a careful selection of essential topics on all three types of circuits, namely, digital, memory, and mixed-signal, each requiring different test and design for testability methods.
Book
Built In Test for VLSI: Pseudorandom Techniques
TL;DR: Digital Testing and the Need for Testable design Principles of Testable Design Pseudorandom Sequence Generators Test Response Compression Techniques and Limitations and Other Concerns of Random Pattern Testing Test System Requirements for Built-In Test Appendix References Index.
Book
VLSI Test Principles and Architectures: Design for Testability (Systems on Silicon)
TL;DR: This book is a comprehensive guide to new DFT methods that will show the readers how to design a testable and quality product, drive down test cost, improve product quality and yield, and speed up time-to-market and time- to-volume.