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Proceedings ArticleDOI

Advanced low power RISC processor design using MIPS instruction set

TL;DR: This paper totally concentrates on designing the architecture in Verilog HDL using the lib library of TSMC Cmos 180nm technology node to solve some of the issues of undesirable hazards in processors.
Abstract: Present era of SOC's comprise analog, digital and mixed signal components housing on the same chip. In this environment processor plays a vital role. As the technology shrinking to sub-micrometer technology node, there exists a huge scope of undesirable hazards in processors. These hazards may lead to disturbance in area, power and timing which deviate from desired quantities. Our paper focuses mainly to solve some of these issues. In-order to tackle these problems, we are introducing the enhanced version of MIPS. Microprocessor without Interlocked Pipeline Stages (MIPS) is a recent architecture into the semi-conductor industry. This paper totally concentrates on designing the architecture in Verilog HDL. The design had been simulated and synthesized in Nc-launch and RTL-compiler licensed by cadence Inc respectively. The physical design of synthesized architecture had been carried on by Socencounter under slow.lib library of TSMC Cmos 180nm technology node.
Citations
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Proceedings ArticleDOI
16 May 2017
TL;DR: This work can be used as a reference for RISC32 processordevelopers to identify and resolve every possible data hazard that might arise during execution phase within the range of the basic MIPS core instruction set.
Abstract: This paper describes the verification plan on data hazard detection and handling for a 32-bit MIPS ISA (Microprocessor without Interlocked Pipeline Stages Instruction Set Architecture) compatible 5-stage pipeline processor, RISC32 Our work can be used as a reference for RISC32 processordevelopers to identify and resolve every possible data hazard that might arise during execution phase within the range of the basic MIPS core instruction set The techniques used to resolvedata hazard in this paper are data forwarding and pipeline stages stalling When data hazard arises, it is first resolve by using data forwarding If the problem persists, we use pipeline stages stalling then only follow by another data forwarding to resolve the data hazard This combination will reduce the impact of data hazard on the processor throughput, instead of only using the pipeline stages stalling This paper delivers a comprehensive analysis and the development of the data hazard resolving blocks that are able to resolve data hazard arises

12 citations

01 Jan 2009
TL;DR: A modified architecture is proposed that leads to significant power reduction by reducing unwanted transitions in a low power five-stage parallel pipelined structure of a MIPS-32 compatible CPU.
Abstract: This paper presents the design and implementation of a low power five-stage parallel pipelined structure of a MIPS-32 compatible CPU. The various blocks include the data-path, control logic, data and program memories. Hazard detection and data forwarding units have been included for efficient implementation of the pipeline. A modified architecture is proposed that leads to significant power reduction by reducing unwanted transitions. Verilog design followed by synthesis on to Xilinx spartan-3E FPGA was done. On-chip distributed memory of Spartan-3E was used for the data and the program memory implementations.

7 citations

Proceedings ArticleDOI
01 Jan 2018
TL;DR: The criterion one must consider for the choice of an embedded system from the plethora of systems available in the market and the choiceof control technique for different robotic applications is discussed.
Abstract: Micro controller contains one or more processor cores along with peripheral devices and memory. Micro-controllers find extensive use in embedded system applications such as automobile engine control systems, bio-medical devices, electronic appliances, etc. They are specific to a particular task, are small and compact in size, and consume less power; all of these features have resulted in the ubiquitous deployment of micro-controllers in various devices. However, it must be noted that a microcontroller is a Control Circuit, and not a Driving Circuit. This statement is supported by the fact that the output current of a microcontroller is too small to drive a motor connected to it directly; in fact, this is an unpropitious experiment and can damage the microcontroller. The microcontroller controls the working of actuators connected to it by following the logic coded onto it, and in this sense, forms the very brain of the embedded system. But in order to drive the motor, we need a type of switch (MOSFET, Relay, etc.) which can take the small output current of the microcontroller and control the power source to the motor. Essentially, a microcontroller accepts real-time inputs and generates an output control signal as per the rules and predefined logical deductions, in the prescribed algorithm. This paper discusses the criterion one must consider for the choice of an embedded system from the plethora of systems available in the market and the choice of control technique for different robotic applications.

4 citations


Additional excerpts

  • ...Due to the presence of MAC unit and pipelining architectures, DSPs deliver maximum work per clock cycle [1]....

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Journal ArticleDOI
TL;DR: A RISC processor using MIPS instruction set architecture which supports multifunctioning is designed, and a principle on how performance can be improved in the context of microprocessor Units applications is presented.
Abstract: Today’s world suggests multifunction in each products. This paper design a RISC processor using MIPS instruction set architecture which supports multifunctioning. Dynamic Reconfiguration refers to the ability of the Processor to update its internal Instruction Decode and Execute stage in order to support new functions, while the system is running. This project presents a principle on how performance can be improved in the context of microprocessor Units applications, using the MIPS instruction set.

1 citations


Cites methods from "Advanced low power RISC processor d..."

  • ...In the scheme presented in [1] ensure the power reduction of a RISC processor ....

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Proceedings ArticleDOI
14 Jun 2023
TL;DR: In this article , a five-stage pipelined MIPS processor with 16 instructions with a total of 49 variants, 5 pipeline stages, and a hazard unit is tested using constrained random verification and for implementing verification techniques in System Verilog Unified Verification Methodology.
Abstract: The Million Instructions Per Second (MIPS) processor design is one of the very earlier foundation of designs for modern-day processor. This brings various different basic concepts of modern-day computing such as Pipelining, Data Dependency handling, and forwarding to one place to enhance the capabilities and speed of processing. This research work proposes to verify few functionalities of a five-stage pipelined MIPS processor. The design under test comes with a total of 16 instructions with a total of 49 variants, 5 pipeline stages, and a hazard unit. Also, this research study presents the verification of this design. The functionality of each instruction is tested using Constrained Random Verification and for implementing verification techniques in System Verilog Unified Verification Methodology (UVM) is used.
References
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Book
01 Jan 1993
TL;DR: The third edition of the book as mentioned in this paper has been updated with new pedagogical features, such as new information and challenging exercises for the advanced student, as well as a complete index of the material in the book and on the CD appears in the printed index.
Abstract: What's New in the Third Edition, Revised Printing The same great book gets better! This revised printing features all of the original content along with these additional features:. Appendix A (Assemblers, Linkers, and the SPIM Simulator) has been moved from the CD-ROM into the printed book. Corrections and bug fixesThird Edition featuresNew pedagogical features.Understanding Program Performance -Analyzes key performance issues from the programmer's perspective .Check Yourself Questions -Helps students assess their understanding of key points of a section .Computers In the Real World -Illustrates the diversity of applications of computing technology beyond traditional desktop and servers .For More Practice -Provides students with additional problems they can tackle .In More Depth -Presents new information and challenging exercises for the advanced student New reference features .Highlighted glossary terms and definitions appear on the book page, as bold-faced entries in the index, and as a separate and searchable reference on the CD. .A complete index of the material in the book and on the CD appears in the printed index and the CD includes a fully searchable version of the same index. .Historical Perspectives and Further Readings have been updated and expanded to include the history of software R&D. .CD-Library provides materials collected from the web which directly support the text. In addition to thoroughly updating every aspect of the text to reflect the most current computing technology, the third edition .Uses standard 32-bit MIPS 32 as the primary teaching ISA. .Presents the assembler-to-HLL translations in both C and Java. .Highlights the latest developments in architecture in Real Stuff sections: -Intel IA-32 -Power PC 604 -Google's PC cluster -Pentium P4 -SPEC CPU2000 benchmark suite for processors -SPEC Web99 benchmark for web servers -EEMBC benchmark for embedded systems -AMD Opteron memory hierarchy -AMD vs. 1A-64 New support for distinct course goals Many of the adopters who have used our book throughout its two editions are refining their courses with a greater hardware or software focus. We have provided new material to support these course goals: New material to support a Hardware Focus .Using logic design conventions .Designing with hardware description languages .Advanced pipelining .Designing with FPGAs .HDL simulators and tutorials .Xilinx CAD tools New material to support a Software Focus .How compilers work .How to optimize compilers .How to implement object oriented languages .MIPS simulator and tutorial .History sections on programming languages, compilers, operating systems and databases On the CD.NEW: Search function to search for content on both the CD-ROM and the printed text.CD-Bars: Full length sections that are introduced in the book and presented on the CD .CD-Appendixes: Appendices B-D .CD-Library: Materials collected from the web which directly support the text .CD-Exercises: For More Practice provides exercises and solutions for self-study.In More Depth presents new information and challenging exercises for the advanced or curious student .Glossary: Terms that are defined in the text are collected in this searchable reference .Further Reading: References are organized by the chapter they support .Software: HDL simulators, MIPS simulators, and FPGA design tools .Tutorials: SPIM, Verilog, and VHDL .Additional Support: Processor Models, Labs, Homeworks, Index covering the book and CD contents Instructor Support Instructor support provided on textbooks.elsevier.com:.Solutions to all the exercises .Figures from the book in a number of formats .Lecture slides prepared by the authors and other instructors .Lecture notes

1,521 citations

Proceedings Article
01 Dec 2009
TL;DR: In this paper, the design and implementation of a low power five-stage parallel pipelined structure of a MIPS-32 compatible CPU is presented, where various blocks include the data-path, control logic, data and program memories.
Abstract: This paper presents the design and implementation of a low power five-stage parallel pipelined structure of a MIPS-32 compatible CPU. The various blocks include the data-path, control logic, data and program memories. Hazard detection and data forwarding units have been included for efficient implementation of the pipeline. A modified architecture is proposed that leads to significant power reduction by reducing unwanted transitions. Verilog design followed by synthesis on to Xilinx spartan-3E FPGA was done. On-chip distributed memory of Spartan-3E was used for the data and the program memory implementations.

24 citations

Proceedings ArticleDOI
22 Sep 2009
TL;DR: This paper significantly reduced stall by introducing pre-fetching unit, which reduces stall by concurrently reading three instructions and check their possibility of stall, and employs forwarding and memory hazard detection units to further reduce stall.
Abstract: This paper describes the design of a MIPS architecture with a small number of stall. Stall frequently happens in pipeline architecture which results in larger clock cycles. In this paper we significantly reduced stall by introducing pre-fetching unit. This unit reduces stall by concurrently reading three instructions and check their possibility of stall. If stall is detected, this unit then changes the sequence of executed instructions. Furthermore, we also employ forwarding and memory hazard detection units to further reduce stall. In order to increase the processor functionality and performances, especially for RSA security application, we include two new instructions 32-bit mult and mod. The design has been successfully implemented in FPGA DE2 Board (Terasic) and standard call CMOS 0.13u. As system verification, we successfully execute bubble sort program and RSA encryption. The system implementation reach the maximum frequency of 714 MHz.

21 citations

Proceedings ArticleDOI
01 Jan 2012
TL;DR: The design and analysis of the functional units of RISC based MIPS architecture, which includes the Instruction fetch unit, instruction decode unit, execution unit, data memory and control unit, attempts to achieve high performance with the use of a simplified instruction set.
Abstract: This paper describes the design and analysis of the functional units of RISC based MIPS architecture. The functional units includes the Instruction fetch unit, instruction decode unit, execution unit, data memory and control unit. The functions of these modules are implemented by pipeline without any interlocks and are simulated successfully on Modelsim 6.3f and Xilinx 9.2i. It also attempts to achieve high performance with the use of a simplified instruction set. KeywordsMIPS, RISC, Pipelining, Memory.

1 citations


"Advanced low power RISC processor d..." refers background or methods in this paper

  • ...Compilation of all the Blocks Hence by combining all the blocks together into one total block diagram gives MIPS Multicore Data path[3][2]....

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  • ...When the next instruction is prevented from being executed in the respective clock cycle is called a Hazard [3]....

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  • ...Adding Pipeline to the Stages[3] To add Pipeline to the block, it needs to be divided into parts based on our requirement....

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