Proceedings ArticleDOI
Algorithms for high performance two-layer channel routing
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TLDR
This paper has developed heuristic algorithms for computing reduced crosstalk two-layer channel routing solutions for simplest as well as general channel instances and the results obtained are highly encouraging.Abstract:
Crosstalk minimization is one of the most important high performance aspects in interconnecting VLSI circuits. With advancement of fabrication technology, devices and interconnecting wires are placed in closer proximity and circuits operate at higher frequencies. This results in crosstalk between wire segments. Crosstalk minimization problem for the reserved two-layer Manhattan channel routing is NP-hard, even if the channel instances are free from any vertical constraint (simplest channel instances). In this paper we have developed heuristic algorithms for computing reduced crosstalk two-layer channel routing solutions for simplest as well as general channel instances. In general, the results obtained are highly encouraging.read more
Citations
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Hardness of crosstalk minimization in two-layer channel routing
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References
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Book
Algorithmic graph theory and perfect graphs
TL;DR: This new Annals edition continues to convey the message that intersection graph models are a necessary and important tool for solving real-world problems and remains a stepping stone from which the reader may embark on one of many fascinating research trails.
Proceedings ArticleDOI
Wire routing by optimizing channel assignment within large apertures
TL;DR: The purpose of this paper is to introduce a new wire routing method for two layer printed circuit boards based on the newly developed channel assignment algorithm and requires many via holes.
Journal ArticleDOI
Efficient Algorithms for Channel Routing
Takeshi Yoshimura,Ernest S. Kuh +1 more
TL;DR: Two new algorithms merge nets instead of assigning horizontal tracks to individual nets to route a specified net list between two rows of terminals across a two-layer channel in the layout design of LSI chips.
Algorithms for integrated circuit layout: an analytic approach
TL;DR: The major result presented in this dissertation is a polynomial time algorithm for a restricted case of the routing problem, which minimizes the area of a rectangle circumscribing the component and the wire paths.
Journal ArticleDOI
A general greedy channel routing algorithm
TL;DR: It is shown that track-oriented greedy algorithms can be modified to solve other channel routing problems, and modified algorithms have good performance and show strong potential to outperform existing algorithms.