All-metal electrodes vertical gate-all-around device with self-catalyzed selective grown InAs NWs array
19 Apr 2018-Science in China Series F: Information Sciences (Science China Press)-Vol. 61, Iss: 6, pp 062404
TL;DR: The first all-metal electrodes vertical gate-allaround (VGAA) FET fabricated using self-catalyzed selective grown InAs NWs array grown by metal organic chemical vapor deposition is reported.
Abstract: With the scaling down of field-effect transistors (FETs) to improve their performance, 3D vertical surrounding gate structure has drawn great attention. On the other hand, concerning the channel materials, InAs nanowires (NWs) have been demonstrated to have great potential in FET due to their high mobility and other excellent electrical properties. Here, we report the first all-metal electrodes vertical gate-allaround (VGAA) FET fabricated using self-catalyzed selective grown InAs NWs array grown by metal organic chemical vapor deposition. A typical transistor we fabricated has an on-state current larger than 37 μA/μm when the drain voltage and gate voltage are +0.6 V and +3.0 V, respectively, and an on-off ratio over 3 orders of magnitudes. We have measured 34 transistors in total, and most of them have the on-off ratio between 102 and 104. Annealing is observed to improve the contact property, increase the on-state current, but decrease the on-off ratio. The ways to improve the performance of InAs NW VGAA FET are discussed.
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TL;DR: Surrounding-gate transistors using core–multishell nanowire channels with a six-sided, high-electron-mobility transistor structure greatly enhance the on-state current and transconductance while keeping good gate controllability.
Abstract: The fabrication of transistors using vertical, six-sided core–multishell indium gallium arsenide nanowires with an all-surrounding gate on a silicon substrate combines the advantages of a three-dimensional gate architecture with the high electron mobility of the III–V nanowires, drastically enhancing the on-state current and transconductance. In the continuing drive to improve and miniaturize transistors, the microelectronics industry has recently adopted three-dimensional electronic gate structures. Another way of improving transistors is to use semiconductor materials with higher electron mobility than silicon, although this presents significant fabrication challenges. Katsuhiro Tomioka et al. combine the two approaches; they grow, with high precision, vertical, six-sided core–multishell indium gallium arsenide nanowires with an all-surrounding gate on a silicon substrate. The resulting devices demonstrate superior transistor performance with excellent on/off switching behaviour and fast operation. Silicon transistors are expected to have new gate architectures, channel materials and switching mechanisms in ten years’ time1,2,3,4. The trend in transistor scaling has already led to a change in gate structure from two dimensions to three, used in fin field-effect transistors, to avoid problems inherent in miniaturization such as high off-state leakage current and the short-channel effect. At present, planar and fin architectures using III–V materials, specifically InGaAs, are being explored as alternative fast channels on silicon5,6,7,8,9 because of their high electron mobility and high-quality interface with gate dielectrics10. The idea of surrounding-gate transistors11, in which the gate is wrapped around a nanowire channel to provide the best possible electrostatic gate control, using InGaAs channels on silicon, however, has been less well investigated12,13 because of difficulties in integrating free-standing InGaAs nanostructures on silicon. Here we report the position-controlled growth of vertical InGaAs nanowires on silicon without any buffering technique and demonstrate surrounding-gate transistors using InGaAs nanowires and InGaAs/InP/InAlAs/InGaAs core–multishell nanowires as channels. Surrounding-gate transistors using core–multishell nanowire channels with a six-sided, high-electron-mobility transistor structure greatly enhance the on-state current and transconductance while keeping good gate controllability. These devices provide a route to making vertically oriented transistors for the next generation of field-effect transistors and may be useful as building blocks for wireless networks on silicon platforms.
704 citations
TL;DR: In this paper, a scaling theory for fully-depleted, cylindrical MOSFET's was presented. But the scaling theory was derived from the cylinrical form of Poisson's equation by assuming a parabolic potential in the radial direction.
Abstract: We present a scaling theory for fully-depleted, cylindrical MOSFET's. This theory was derived from the cylindrical form of Poisson's equation by assuming a parabolic potential in the radial direction. Numerical device simulation data for subthreshold slope and DIBL were compared to the model to validate the formula. By employing the scaling theory a comparison with double-gate (DG) MOSFET's was carried out illustrating an improvement of up to 40% in the minimum effective channel length for the cylindrical device.
551 citations
TL;DR: Temperature-dependent I-V and C-V spectroscopy of single InAs nanowire field-effect transistors were utilized to directly shed light on the intrinsic electron transport properties as a function of nanowires radius, serving as a versatile and powerful platform for in-depth characterization of nanoscale, electronic materials.
Abstract: Temperature-dependent I−V and C−V spectroscopy of single InAs nanowire field-effect transistors were utilized to directly shed light on the intrinsic electron transport properties as a function of nanowire radius. From C−V characterizations, the densities of thermally activated fixed charges and trap states on the surface of untreated (i.e., without any surface functionalization) nanowires are investigated while enabling the accurate measurement of the gate oxide capacitance, therefore leading to the direct assessment of the field-effect mobility for electrons. The field-effect mobility is found to monotonically decrease as the radius is reduced to <10 nm, with the low temperature transport data clearly highlighting the drastic impact of the surface roughness scattering on the mobility degradation for miniaturized nanowires. More generally, the approach presented here may serve as a versatile and powerful platform for in-depth characterization of nanoscale, electronic materials.
391 citations
TL;DR: A model that allows accurate estimation of characteristic NW parameters, including carrier field-effect mobility and carrier concentration by taking into account series and leakage resistances, interface state capacitance, and top-gate geometry is developed.
Abstract: Single-crystal InAs nanowires (NWs) are synthesized using metal-organic chemical vapor deposition (MOCVD) and fabricated into NW field-effect transistors (NWFETs) on a SiO(2)/n(+)-Si substrate with a global n(+)-Si back-gate and sputtered SiO(x)/Au underlap top-gate. For top-gate NWFETs, we have developed a model that allows accurate estimation of characteristic NW parameters, including carrier field-effect mobility and carrier concentration by taking into account series and leakage resistances, interface state capacitance, and top-gate geometry. Both the back-gate and the top-gate NWFETs exhibit room-temperature field-effect mobility as high as 6580 cm(2) V(-1) s(-1), which is the lower-bound value without interface-capacitance correction, and is the highest mobility reported to date in any semiconductor NW.
328 citations
TL;DR: In this article, the authors modeled the transport in the nanowire as in a metal-semiconductor-metal structure involving two Schottky barriers and a resistor in between these barriers.
Abstract: Electrical transport measurements were conducted on semiconducting nanowires and three distinct current-voltage (I-V) characteristics were observed, i.e., almost symmetric, almost rectifying, and almost linear. These I-V characteristics were modeled by treating the transport in the nanowire as in a metal-semiconductor-metal structure involving two Schottky barriers and a resistor in between these barriers, and the transport is shown to be dominated by the reverse-biased Schottky barrier under low bias and by the semiconducting nanowire at large bias. In contrast to the conventional Schottky diode, the reverse current in the nano-Schottky barrier structure is not negligible and the current is largely tunneling rather than thermionic. Experimental I-V curves are reproduced very well using our model, and a method for extracting nanowire resistance, electron density, and mobility is proposed and applied to ZnO, CdS, and Bi2S3 nanowires.
276 citations