Ambient field effects on the current-voltage characteristics of nanowire field effect transistors
TL;DR: In this paper, the effects of ambient field from the gate and drain contacts on the currentvoltage characteristics of a vertical nanowire field effect transistor having a lightly doped ungated length near the drain were investigated.
Abstract: We investigate the effects of ambient field from the gate and drain contacts on the current-voltage characteristics of a vertical nanowire field effect transistor having a lightly doped ungated length near the drain. Such a device is suitable for high voltage (tens of volts) applications. It is shown that the ambient field enhances the carrier concentration and divides the ungated region into gate-controlled and drain-controlled sections, controllable by the drain contact size and bias-voltages. These phenomena have a significant impact on the drain breakdown voltage, saturation voltage, saturation current and output resistance. The effects are established with the help of measured data and numerically calculated current-voltage curves and field lines.
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TL;DR: In this article, the possibility to vertically integrate SiGe nanowires in order to use them as vertical channel for field effect transistors (FETs) was demonstrated and a threshold voltage close to 3.9 V was reported.
Abstract: We demonstrate in this paper the possibility to vertically integrate SiGe nanowires in order to use them as vertical channel for field-effect transistors (FETs). We report a threshold voltage close to 3.9 V, an ION/IOFF ratio of 104. The subthreshold slope was estimated to be around 0.9 V/decade and explained by a high traps density at the nanowire core/oxide shell interface with an estimated density of interface traps Dit ∼ 1.2 × 1013 cm−2 eV−1. Comparisons are made with both vertical Si and horizontal SiGe FETs performances.
27 citations
TL;DR: In this paper, the authors report the fabrication and electrical characterization of Vertical Gate All Around Field Effect Transistors (GAA-FET) using nonintentionally doped Silicon NanoWires (SiNWs) grown by Chemical Vapour Deposition (CVD) using the VLS mechanism as conduction channel.
19 citations
TL;DR: The first all-metal electrodes vertical gate-allaround (VGAA) FET fabricated using self-catalyzed selective grown InAs NWs array grown by metal organic chemical vapor deposition is reported.
Abstract: With the scaling down of field-effect transistors (FETs) to improve their performance, 3D vertical surrounding gate structure has drawn great attention. On the other hand, concerning the channel materials, InAs nanowires (NWs) have been demonstrated to have great potential in FET due to their high mobility and other excellent electrical properties. Here, we report the first all-metal electrodes vertical gate-allaround (VGAA) FET fabricated using self-catalyzed selective grown InAs NWs array grown by metal organic chemical vapor deposition. A typical transistor we fabricated has an on-state current larger than 37 μA/μm when the drain voltage and gate voltage are +0.6 V and +3.0 V, respectively, and an on-off ratio over 3 orders of magnitudes. We have measured 34 transistors in total, and most of them have the on-off ratio between 102 and 104. Annealing is observed to improve the contact property, increase the on-state current, but decrease the on-off ratio. The ways to improve the performance of InAs NW VGAA FET are discussed.
1 citations
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TL;DR: In this article, an analytic charge model for surrounding-gate MOSFETs is presented, which is based on closed-form solution of Poisson's equation, current continuity equation, and Ward-Dutton linear charge partition.
Abstract: This paper presents an analytic charge model for surrounding-gate MOSFETs. Without the charge sheet approximation, the model is based on closed-form solution of Poisson's equation, current continuity equation, and Ward-Dutton linear charge partition. It continuously covers all the operation regions, i.e., linear, saturation, and subthreshold, with unique analytic expressions. The physics-based nature makes this model free of fitting parameters and hence predictive. In addition, it is inherently not source-referenced to avoid asymmetries. It is shown that the current-voltage characteristics generated by this model agree with the numerical simulation results
83 citations
TL;DR: In this paper, the authors numerically investigate certain unique properties of nanowire-metal contacts and demonstrate that contact resistivity increases as the radius shrinks, and the underlying cause for this size effect is identified as the strong fringing field effects.
Abstract: Metal contacts play an important role in nanowire devices and are expected to exhibit qualitatively different properties from those of planar contacts due to small contact cross sections. We numerically investigate certain unique properties of nanowire-metal contacts and demonstrate that contact resistivity increases as nanowire radius shrinks. This increase is more significant for nanowire-three-dimensional metal contacts than for nanowire-one-dimensional metal contacts. The underlying cause for this size effect is identified as the strong fringing field effects, which become more significant as temperature decreases. Our simulation provides a more complete understanding of the size effects on nanowire-metal contacts.
57 citations
TL;DR: In this paper, the drain current, transconductance, output conductance, terminal charges, and capacitances of a silicon-based nanowire FET (SNWT) compact model is developed for circuit simulation.
Abstract: A silicon-based nanowire FET (SNWT) compact model is developed for circuit simulation. Starting from the solution of poisson's equation, an accurate inversion charge expression is derived for SNWTs with arbitrary body doping concentration. The drain current, transconductance, output conductance, terminal charges, and capacitances are then calculated based on fundamental device physics. Short-channel and quantum effects have been included in the model in a self-consistent way. Comparison between the numerical simulation and analytical calculation shows that the proposed model is valid for all operation regions of SNWTs with different dimensions and channel doping. The model has been implemented in circuit simulators by Verilog-A, and its application in circuit simulation is also demonstrated.
31 citations
TL;DR: This work demonstrates highly reproducible silicon nanowire diodes fabricated with a fully VLSI compatible etching technology, and suggests that this technology is suitable for incorporating nanowires-based functionalities into future integrated circuits.
Abstract: We demonstrate highly reproducible silicon nanowire diodes fabricated with a fully VLSI compatible etching technology, with diameters down to 30 nm. A contact technology based on recrystallized polysilicon enables specific contact resistances as low as rho approximately 10-7 Omega cm2. Our devices show a strongly diameter-dependent breakdown voltage at reverse bias, which we explain in terms of the influence of the surrounding dielectric. We suggest that this technology is suitable for incorporating nanowire-based functionalities into future integrated circuits.
28 citations
TL;DR: In this paper, the conductivity of thin wires was shown to depend noticeably on the properties and particularly the dimensionality of contacts, and the spatial distribution of nonequilibrium carriers was found for different signal frequencies ω.
Abstract: The conductivity of thin wires was shown to depend noticeably on the properties and, particularly, dimensionality of contacts. Two- and one-dimensional contacts create a strongly nonuniform electric field in a wire which, in turn, causes the redistribution of electron density along a wire and nonlinear current–voltage characteristic. The particular shape of the latter has been calculated for both Ohmic and Schottky contacts of different dimensionality. The case of ac applied voltage is also considered. Spatial distribution of nonequilibrium carriers is found for different signal frequencies ω. The wire conductivity is shown to increase with ω for any type of low-dimensional contacts.
20 citations