An 8Gbps 2.5mW on-chip pulsed-current-mode transmission line interconnect with a stacked-switch Tx
18 Nov 2008-pp 474-477
TL;DR: This paper proposes a high energy-efficient pulsed-current-mode transmission line interconnect (PTLI) for on-chip networks and introduces the stacked-switch transmitter (Tx) for saving a static power of Tx.
Abstract: This paper proposes a high energy-efficient pulsed-current-mode transmission line interconnect (PTLI) for on-chip networks. The stacked-switch transmitter (Tx) is introduced for saving a static power of Tx. Point-to-point and multi-drop PTLIs are demonstrated, and simulation results show that the 5-mm-long PTLI with six Txs and six receivers (Rxs) can achieve multi-drop signaling. The point-to-point PTLI with a 5-mm-long transmission line is fabricated by using 90 nm Si CMOS process and can transmit 8 Gbps signals with power consumption of 2.5 mW and a delay of 164 ps.
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TL;DR: In this article, an integrated optical link using a membrane distributedfeedback (DFB) laser and a p-i-n photodiode (PD) in a butt-jointed built-in coupling geometry is presented.
Abstract: On-chip optical interconnection is a promising technology for wiring future large-scale integrated circuits, as a means to mitigate the considerable power dissipation of traditional wiring layers. Here, we fabricate an integrated optical link using a membrane distributed-feedback (DFB) laser and a p-i-n photodiode (PD) in a butt-jointed built-in coupling geometry. The optical link is formed on a Si substrate by benzocyclobutene bonding. The integrated DFB laser shows a low-threshold current of 0.48 mA. Light transmission between the DFB laser and the p-i-n PD is confirmed with static measurements of the optical link. The optical link has a 3-dB bandwidth of 11.3 GHz at a 2.73 mA DFB laser bias current and a –3 V p-i-n PD bias voltage. A data transmission experiment of the optical link is performed, using a nonreturn to zero, pseudorandom-bit-sequence with a word length of 231-1 signals. With a DFB laser bias current of 2.5 mA, 10 Gbit/s data transmission with a bit-error-rate of 6 × 10–7 is successfully achieved.
13 citations
Cites background from "An 8Gbps 2.5mW on-chip pulsed-curre..."
...Novel type on-chip electrical interconnection technologies such as carbon-nanotubes [4] and high-speed transmission lines [5]–[7] have been proposed as approaches ca-...
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TL;DR: In line with variation-aware design, a novel ingenious method of measuring variations in subthreshold characteristics is described and an on-chip transmission line interconnect developed for global wiring is discussed.
Abstract: There are many challenges inherent in the design of nano-CMOS. This paper describes our recent work relating to the physical design of CMOS circuits. First, in line with variation-aware design, a novel ingenious method of measuring variations in subthreshold characteristics is described. Next, recent RF CMOS issues and approaches to nano-CMOS are discussed. Finally, an on-chip transmission line interconnect developed for global wiring is discussed.
9 citations
Cites background or methods from "An 8Gbps 2.5mW on-chip pulsed-curre..."
...This paper discusses the pulsed current mode circuit, which features low power consumption [34]....
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...Details of the operation of Tx and Rx are described elsewhere [34]....
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...To further improve TLI, we have recently developed the pulse current mode (PCM) circuit [34] and the equalizing technique [35]....
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TL;DR: In this paper, the temperature dependence of a GaInAsP/InP membrane distributed-reflector laser bonded on a Si substrate was measured, which showed a low threshold current (0.29 mA) and a relatively high differential quantum efficiency (23% from the front side) at 20 °C.
Abstract: The temperature dependence of a GaInAsP/InP membrane distributed-reflector laser bonded on a Si substrate — which showed a low threshold current (0.29 mA) and a relatively high differential quantum efficiency (23% from the front side) at 20 °C — was measured. A characteristic temperature of the threshold current, T 0, of 84 K and a sub-mA threshold current operation up to 90 °C were obtained under a continuous-wave (CW) condition. Furthermore, single-mode operation up to 80 °C was also obtained.
7 citations
01 Jan 2018
TL;DR: In this paper, theoretical and experimental characteristics of lateral current injection (LCI)-type membrane distributed feedback (DFB) and distributed reflector (DR) lasers intended for ultra-low power consumption optical communication systems such as on-chip optical interconnections are presented.
Abstract: In this chapter, theoretical and experimental characteristics of lateral current injection (LCI)-type membrane distributed feedback (DFB) and distributed reflector (DR) lasers intended for ultra-low power consumption optical communication systems such as on-chip optical interconnections are presented. First, fundamentals of the membrane laser such as an enhancement of the optical confinement factor of the active region and its effect on threshold current and modulation speed are explained. Then the energy cost analysis of the membrane DR laser is discussed from aspects of an output power and modulation speed. Fabrication and static and dynamic lasing characteristics of membrane DFB and DR lasers bonded on a Si substrate are also explained. A p-i-n membrane photodiode and its integration with the membrane DFB laser are explained.
1 citations
Cites background from "An 8Gbps 2.5mW on-chip pulsed-curre..."
...…the total chip power dissipation became grossly affected by the metal wiring (Banerjee and Mehrotra, 2001; Borkar and Chien, 2011; Ho et al., 2001), and high-speed signal transmissions with an energy cost close to 0.3 pJ/bit were demon- strated in 2008 (Maekawa et al., 2008; Mensink et al., 2007)....
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TL;DR: The authors propose a hybrid transceiver and an energy-efficient link architecture for bidirectional multipoint-to-multipoint signalling across on-chip global interconnect that eliminates the need for passive termination for bandwidth enhancement by means of active termination, reducing the required transmitter signalling current drastically and hence, improving the overall energy efficiency of the link.
Abstract: The authors propose a hybrid transceiver and an energy-efficient link architecture for bidirectional multipoint-to-multipoint signalling across on-chip global interconnect. The proposed link architecture eliminates the need for passive termination for bandwidth enhancement by means of active termination, reducing the required transmitter signalling current drastically and hence, improving the overall energy efficiency of the link. Also, compared to existing passive terminated interconnect with current-mode receivers at all the points, the proposed link deploys low impedance current-mode receivers providing active terminations at both the ends of the interconnect and high-impedance voltage-mode receivers, which do not consume any portion of the signalling current, at the intermediate nodes of the interconnect which further lowers the required transmitter signalling current. A mixed-mode or hybrid transceiver architecture has been proposed for the aforementioned link, which can act either as a current-mode transmitter or a current-mode receiver or a voltage-mode receiver. The architecture has been implemented in 0.18-μm complementary metal oxide semiconductor technology for an interconnect of length 4 mm and having five transceiver nodes. The total energy efficiency of the architecture is 0.70 pJ/b for a speed of 3.0 Gb/s.
1 citations
References
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TL;DR: In this paper, an energy-efficient NoC is pre-sented for possible application to high-performance system-on-chip (SoC) design, which incorporates heterogeneous intellectual prop- erties (IPs) such as multiple RISCs and SRAMs, a reconfigurable logic array, an off-chip gateway, and a 1.6GHz phase-locked loop (PLL).
Abstract: An energy-efficient network-on-chip (NoC) is pre- sented for possible application to high-performance system-on- chip (SoC) design. It incorporates heterogeneous intellectual prop- erties (IPs) such as multiple RISCs and SRAMs, a reconfigurable logic array, an off-chip gateway, and a 1.6-GHz phase-locked loop (PLL). Its hierarchically-star-connected on-chip network provides the integrated IPs, which operate at different clock frequencies, with packet-switched serial-communication infrastructure. Var- ious low-power techniques such as low-swing signaling, partially activated crossbar, serial link coding, and clock frequency scaling are devised, and applied to achieve the power-efficient on-chip communications. The 5 5m m chip containing all the above features is fabricated by 0.18- m CMOS process and successfully measured and demonstrated on a system evaluation board where multimedia applications run. The fabricated chip can deliver 11.2-GB/s aggregated bandwidth at 1.6-GHz signaling frequency. The chip consumes 160 mW and the on-chip network dissipates less than 51 mW.
160 citations
TL;DR: An energy-efficient network-on-chip (NoC) is presented, which incorporates heterogeneous intellectual properties such as multiple RISCs and SRAMs, a reconfigurable logic array, an off-chip gateway, and a 1.6-GHz phase-locked loop (PLL) to achieve the power-efficient on-chip communications.
Abstract: An energy-efficient network-on-chip (NoC) is presented for possible application to high-performance system-on-chip (SoC) design. It incorporates heterogeneous intellectual properties (IPs) such as multiple RISCs and SRAMs, a reconfigurable logic array, an off-chip gateway, and a 1.6-GHz phase-locked loop (PLL). Its hierarchically-star-connected on-chip network provides the integrated IPs, which operate at different clock frequencies, with packet-switched serial-communication infrastructure. Various low-power techniques such as low-swing signaling, partially activated crossbar, serial link coding, and clock frequency scaling are devised, and applied to achieve the power-efficient on-chip communications. The 5 /spl times/5 mm/sup 2/ chip containing all the above features is fabricated by 0.18-/spl mu/m CMOS process and successfully measured and demonstrated on a system evaluation board where multimedia applications run. The fabricated chip can deliver 11.2-GB/s aggregated bandwidth at 1.6-GHz signaling frequency. The chip consumes 160 mW and the on-chip network dissipates less than 51 mW.
156 citations
"An 8Gbps 2.5mW on-chip pulsed-curre..." refers background in this paper
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TL;DR: In this article, the propagation limits of electrical signals for systems built with conventional silicon processing are explored and a design which takes advantage of the inductance-dominated high-frequency regime of on-chip interconnect is shown capable of transmitting data at velocities near the speed of light.
Abstract: The propagation limits of electrical signals for systems built with conventional silicon processing are explored A design which takes advantage of the inductance-dominated high-frequency regime of on-chip interconnect is shown capable of transmitting data at velocities near the speed of light In a 018-/spl mu/m six-level aluminum CMOS technology, an overall delay of 283 ps for a 20-mm-long line, corresponding to a propagation velocity of one half the speed of light in silicon dioxide, has been demonstrated This approach offers a five times improvement in delay over a conventional repeater-insertion strategy
151 citations
"An 8Gbps 2.5mW on-chip pulsed-curre..." refers background in this paper
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TL;DR: A 1.6GHz on-chip network integrating two processors, memories, and an FPGA provides 11.2GB/s bandwidth in 0.18/spl mu/m 6M CMOS technology supporting globally asynchronous, locally synchronous mode and programmable clocking.
Abstract: A 1.6GHz on-chip network integrating two processors, memories, and an FPGA provides 11.2GB/s bandwidth in 0.18/spl mu/m 6M CMOS technology. The 2-level hierarchical star-connected network using serialized low-energy transmission coding, crossbar partial activation and lowswing signaling dissipates 51 mW at 1.6V supporting globally asynchronous, locally synchronous mode and programmable clocking.
95 citations
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TL;DR: In this article, a detailed comparison of optoelectronic versus electrical interconnections for system-on-chip applications is performed in terms of signal latency and power consumption, and it is found that the optolectronic interconnects outperform their electrical counterparts under certain conditions, especially for relatively long lines and multichannel data links.
Abstract: A detailed comparison of optoelectronic versus electrical interconnections for system-on-chip applications is performed in terms of signal latency and power consumption Realistic end-to-end models of both interconnection schemes are employed in order to evaluate critical performance parameters A variety of electrical and optoelectronic interconnection configurations are implemented and simulated using accurate optical device and electronic circuit models integrated under an integrated circuit (IC) design computer-aided design tool Two commercial complementary metal-oxide-semiconductor (CMOS) technologies (08 /spl mu/m and 025 /spl mu/m) are used for the estimation of the signal latency and the power consumption as a function of the interconnection length for the different link configurations It was found that optoelectronic interconnects outperform their electrical counterparts, under certain conditions, especially for relatively long lines and multichannel data links
68 citations