An AC-Coupled Instrumentation Amplifier Achieving 110-dB CMRR at 50 Hz With Chopped Pseudoresistors and Successive-Approximation-Based Capacitor Trimming
01 Jan 2021-IEEE Journal of Solid-state Circuits (Institute of Electrical and Electronics Engineers (IEEE))-Vol. 56, Iss: 1, pp 277-286
TL;DR: A modified chopping structure is proposed to mitigate the mismatch effect of the pseudoresistors, and a successive-approximation based capacitor trimming loop is exploited to enhance the CMRR performance primarily.
Abstract: High common-mode rejection ratio (CMRR) with concurrent electrode offset rejection is essential for physiological signal acquisitions. This article presents a CMRR enhancement technique for ac-coupled instrumentation amplifiers (ACIAs), where the mismatch of passive components limits the CMRR performance primarily. A modified chopping structure is proposed to mitigate the mismatch effect of the pseudoresistors, and a successive-approximation based capacitor trimming loop is exploited. Fabricated in a 0.18- $\mu \text{m}$ CMOS technology, the ACIA draws $2.3~\mu \text{A}$ from a 1.2-V supply and exhibits 3.2- $\mu \text{V}\mathrm {_{rms}}$ input-referred noise over 0.5–400 Hz. The measured prototypes achieve > 110-dB CMRR at 50/60 Hz without any off-chip tuning.
Citations
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TL;DR: In this paper , the authors presented a high commonmode rejection ratio (CMRR), and high power-supply rejection ratio(PSRR) current-mode instrumentation amplifier (CMIA) to overcome the limitations of existing differential voltage second-generation current conveyors (DVCCII)-based CMIAs in achieving high CMRR.
Abstract: Abstract This study presents a high common-mode rejection ratio (CMRR), and high power-supply rejection ratio (PSRR) current-mode instrumentation amplifier (CMIA) to overcome the limitations of existing differential voltage second-generation current conveyors (DVCCII)-based CMIAs in achieving high CMRR. The design is based on a fully differential second-generation current conveyor block with a novel circuit design following by a current subtracting stage. The CMIA is designed and laid out in 130 nm CMOS technology operating under ± 1.2 V supply voltage in Cadence software. The post-layout simulation results show that the CMIA achieves low-frequency voltage and current CMRR- BW of 228.8 dB–10 kHz and 246 dB–10.6 kHz, respectively, with PSRR + /PSRR- of 108.2 dB/99.7 dB, power consumption of 507 µW, and a core area of 0.0015 mm 2 . The unique quality of the circuit is that, it does not need well-matched active blocks, but inherently improves CMRR, bandwidth, and PSRR; hence it gains an excellent choice for integration.
2 citations
01 Jan 2022
TL;DR: In this article , the authors proposed a commonmode replication (CM-REP) technique, which replicates the input common-mode voltage over the front-end amplifier to improve CMRR and input CM impedance simultaneously.
Abstract: High common-mode rejection ratio (CMRR) of an analog front end (AFE) requires high intrinsic CMRR of the front-end amplifier with high input common-mode (CM) impedance. This article presents a common-mode replication (CM-REP) technique, which replicates the input CM voltage over the front-end amplifier. By eliminating the CM current flow and its mismatch effect, CM-REP improves CMRR and input CM impedance simultaneously. Implementation considerations regarding the input CM range, on-chip, and off-chip parasitics have been discussed with practical techniques incorporated with the proposed CM-REP. Fabricated in a 0.18- $\mu \text{m}$ CMOS technology, the measured instrumentation amplifier (IA) exhibits >130-dB CMRR and 50- $\text{G}\Omega $ input CM impedance at 50/60 Hz concurrently. The >110-dB CMRR is achieved with input CM up to 900 mV pp and >102-dB total CMRR (TCMRR) is obtained with 1- $\text{M}\Omega \|$ 10-nF mismatch of source impedance. The prototype consumes $1.86~\mu \text{A}$ from a 1.8-V supply and occupies an active area of 0.227 mm 2 .
2 citations
28 Oct 2022
TL;DR: In this paper , a Capacitively-Coupled Chopper Instrumentation Amplifier (CCIA) with embedded DC feedback is proposed to reduce the noise of system.
Abstract: This paper presents a low noise and low power circuit for neural recording. A Capacitively-Coupled Chopper Instrumentation Amplifier (CCIA) with embedded DC feedback is proposed to reduce the noise of system. Implemented a continuous-time low-pass filter (LPF) at the output of the system and utilized bulk-feedback techniques to increase its output swing. Furthermore, the DC-block and Chopper-Capacitor-Chopper Integrator Based DC Servo Loop (C3IB-DSL) are combined to reduce the interferences. According to experiment, the circuit consumes only 0.3 µW at 1.2 V. In addition, the input-referred noise reached 2.1 µVrms and the noise efficiency factor (NEF) 3.6 at the same time. The proposed CCIA was simulated in a 180n CMOS process.
28 Oct 2022
TL;DR: In this paper , a Capacitively-Coupled Chopper Instrumentation Amplifier (CCIA) with embedded DC feedback is proposed to reduce the noise of system.
Abstract: This paper presents a low noise and low power circuit for neural recording. A Capacitively-Coupled Chopper Instrumentation Amplifier (CCIA) with embedded DC feedback is proposed to reduce the noise of system. Implemented a continuous-time low-pass filter (LPF) at the output of the system and utilized bulk-feedback techniques to increase its output swing. Furthermore, the DC-block and Chopper-Capacitor-Chopper Integrator Based DC Servo Loop (C3IB-DSL) are combined to reduce the interferences. According to experiment, the circuit consumes only 0.3 µW at 1.2 V. In addition, the input-referred noise reached 2.1 µVrms and the noise efficiency factor (NEF) 3.6 at the same time. The proposed CCIA was simulated in a 180n CMOS process.
References
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Abstract: Basic Concepts of Medical Instrumentation Basic Sensors and Principles Amplifiers and Signal Processing The Origin of Biopotentials Biopotential Electrodes Biopotential Amplifiers Blood Pressure and Sound Measurement of Flow and Volume of Blood Measurements of the Respiratory System Chemical Biosensors Clinical Laboratory Instrumentation Medical Imaging Systems Therapeutic and Prosthetic Devices Electrical Safety.
1,674 citations
TL;DR: In this article, a low-noise low-power biosignal amplifiers capable of amplifying signals in the millihertz-to-kilohertz range while rejecting large dc offsets generated at the electrode-tissue interface is presented.
Abstract: There is a need among scientists and clinicians for low-noise low-power biosignal amplifiers capable of amplifying signals in the millihertz-to-kilohertz range while rejecting large dc offsets generated at the electrode-tissue interface. The advent of fully implantable multielectrode arrays has created the need for fully integrated micropower amplifiers. We designed and tested a novel bioamplifier that uses a MOS-bipolar pseudoresistor element to amplify low-frequency signals down to the millihertz range while rejecting large dc offsets. We derive the theoretical noise-power tradeoff limit - the noise efficiency factor - for this amplifier and demonstrate that our VLSI implementation approaches this limit by selectively operating MOS transistors in either weak or strong inversion. The resulting amplifier, built in a standard 1.5-/spl mu/m CMOS process, passes signals from 0.025Hz to 7.2 kHz with an input-referred noise of 2.2 /spl mu/Vrms and a power dissipation of 80 /spl mu/W while consuming 0.16 mm/sup 2/ of chip area. Our design technique was also used to develop an electroencephalogram amplifier having a bandwidth of 30 Hz and a power dissipation of 0.9 /spl mu/W while maintaining a similar noise-power tradeoff.
1,572 citations
TL;DR: This work has shown clear trends in prognosis of Parkinson's disease in patients with central giant cell granuloma, and these trends are likely to continue into the next generation of treatments.
544 citations
07 Aug 2002
TL;DR: A novel bioamplifier that uses a MOS-bipolar pseudo-resistor to amplify signals down to the mHz range while rejecting large dc offsets and it is demonstrated that the VLSI implementation approaches the theoretical noise-power tradeoff limit.
Abstract: There is a need among scientists and clinicians for low-noise, low-power biosignal amplifiers capable of amplifying signals in the mHz to kHz range while rejecting large dc offsets generated at the electrode-tissue interface. The advent of fully-implantable multielectrode arrays has created the need for fully-integrated micropower amplifiers. We designed and tested a novel bioamplifier that uses a MOS-bipolar pseudo-resistor to amplify signals down to the mHz range while rejecting large dc offsets. We derive the theoretical noise-power tradeoff limit - the noise efficiency factor - for this amplifier and demonstrate that our VLSI implementation approaches that limit. The resulting amplifier, built in a standard 1.5/spl mu/m CMOS process, passes signals from 0.1mHz to 7.2kHz with an input-referred noise of 2.2/spl mu/Vrms and a power dissipation of 80/spl mu/W while consuming 0.16mm/sup 2/ of chip area.
489 citations
"An AC-Coupled Instrumentation Ampli..." refers background in this paper
..., with rail-to-rail EDO rejection and robust to EDO variations [15]–[23]....
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27 Nov 2007
TL;DR: The monolithic architect and micropower low-noise low-supply operation could help enable applications ranging from neuroprosthetics to seizure monitors that require a small form factor and battery operation.
Abstract: This paper describes a prototype micropower instrumentation amplifier intended for chronic sensing of neural field potentials (NFPs). NFPs represent the ensemble activity of thousands of neurons and code-useful information for both normal activity and disease states. NFPs are small - of the order of tens of muV- and reside at low bandwidths that make them susceptible to excess noise. Therefore, to ensure the highest fidelity of signal measurement for diagnostic analysis, the amplifier is chopper-stabilized to eliminate 1/f and popcorn noise. The circuit was prototyped in an 0.8 mum CMOS process and consumes under 2.0 muW from a 1.8 V supply. A noise floor of 0.98 muVrms was achieved over a bandwidth from 0.05 to 100 Hz; the noise-efficiency factor of 4.6 is one of the lowest published to date. A flexible on-chip high-pass filter is used to suppress front-end electrode offsets while maintaining relevant physiological data. The monolithic architect and micropower low-noise low-supply operation could help enable applications ranging from neuroprosthetics to seizure monitors that require a small form factor and battery operation. Although the focus of this paper is on neurophysiological sensing, the circuit architecture can be applied generally to micropower sensor interfaces that benefit from chopper stabilization.
447 citations
"An AC-Coupled Instrumentation Ampli..." refers background or methods in this paper
...Note that the DSL here has a much-relaxed design requirement as compared to that for IAs in [5]–[7] and [10]–[14], where the DSLs are used to deal with the EDO which is much larger....
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...Chopping-based techniques improve the CMRR of IAs effectively, including chopper-stabilized capacitively coupled IAs [5]–[12] and current-balancing IAs [13], [14]....
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