An adaptive continuous-time incremental Σ∆ ADC for neural recording implants
01 Feb 2019-International Journal of Circuit Theory and Applications (John Wiley & Sons, Ltd)-Vol. 47, Iss: 2, pp 187-203
TL;DR: An analog‐to‐digital converter (ADC) with adaptive resolution is presented for wireless neural recording implants and achieves 8‐bit or 3‐bit resolution adaptively with 10 kHz bandwidth while the average power consumption is less than 1.89 μW from a single 1‐V power supply.
Abstract: Int J Circ Theor Appl. 2019;47:187–203. Summary In this paper, an analog‐to‐digital converter (ADC) with adaptive resolution is presented for wireless neural recording implants. The resolution of the ADC is changed according to the neural signal content, and for this purpose, a continuous‐time (CT) incremental sigma‐delta (IΣΔ) modulator is employed. The ADC digitizes the action potential (AP) and background noise (B‐noise) with 8‐bit and 3‐bit resolutions, respectively. An automatic AP detector is used to separate the APs from the B‐noise in order to select one of the two proportional resolutions. The power dissipation and output data rate of the ADC are reduced by using this technique. Analytical calculations and behavioral simulation results are provided to evaluate the performance of the proposed ADC. To further confirm its efficiency, the circuit‐level implementation of the CT IΣΔ ADC is presented in Taiwan Semiconductor Manufacturing Company (TSMC) 90‐nm complementary metal‐oxide semiconductor (CMOS) process. According to the simulation results, the proposed ADC achieves 8‐bit or 3‐bit resolution adaptively with 10 kHz bandwidth while the average power consumption is less than 1.89 μW from a single 1‐V power supply.
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TL;DR: This paper surveys multi-channel neural recording implants, investigates main available neural recording circuit and system architectures, and presents the various dedicated ADC structures, as well as an overview of main data compression methods.
Abstract: The recently growing progress in neuroscience research and relevant achievements, as well as advancements in the fabrication process, have increased the demand for neural interfacing systems. Brain–machine interfaces (BMIs) have been revealed to be a promising method for the diagnosis and treatment of neurological disorders and the restoration of sensory and motor function. Neural recording implants, as a part of BMI, are capable of capturing brain signals, and amplifying, digitizing, and transferring them outside of the body with a transmitter. The main challenges of designing such implants are minimizing power consumption and the silicon area. In this paper, multi-channel neural recording implants are surveyed. After presenting various neural-signal features, we investigate main available neural recording circuit and system architectures. The fundamental blocks of available architectures, such as neural amplifiers, analog to digital converters (ADCs) and compression blocks, are explored. We cover the various topologies of neural amplifiers, provide a comparison, and probe their design challenges. To achieve a relatively high SNR at the output of the neural amplifier, noise reduction techniques are discussed. Also, to transfer neural signals outside of the body, they are digitized using data converters, then in most cases, the data compression is applied to mitigate power consumption. We present the various dedicated ADC structures, as well as an overview of main data compression methods.
36 citations
Cites background from "An adaptive continuous-time increme..."
...Sigma-Delta modulators are also utilized in neural recording applications due to the low-frequency bandwidth of neural signals [98,99]....
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TL;DR: A power-efficient complementary metal-oxide-semiconductor (CMOS) neural signal-recording read-out circuit for multichannel neuromodulation implants and a successive approximation register analog-to-digital converter (SAR-ADC) for recording and digitizing neural signal data to transmit to a remote receiver.
Abstract: This paper presents a power-efficient complementary metal-oxide-semiconductor (CMOS) neural signal-recording read-out circuit for multichannel neuromodulation implants. The system includes a neural amplifier and a successive approximation register analog-to-digital converter (SAR-ADC) for recording and digitizing neural signal data to transmit to a remote receiver. The synthetic neural signal is generated using a LabVIEW myDAQ device and processed through a LabVIEW GUI. The read-out circuit is designed and fabricated in the standard 0.5 μμm CMOS process. The proposed amplifier uses a fully differential two-stage topology with a reconfigurable capacitive-resistive feedback network. The amplifier achieves 49.26 dB and 60.53 dB gain within the frequency bandwidth of 0.57–301 Hz and 0.27–12.9 kHz to record the local field potentials (LFPs) and the action potentials (APs), respectively. The amplifier maintains a noise–power tradeoff by reducing the noise efficiency factor (NEF) to 2.53. The capacitors are manually laid out using the common-centroid placement technique, which increases the linearity of the ADC. The SAR-ADC achieves a signal-to-noise ratio (SNR) of 45.8 dB, with a resolution of 8 bits. The ADC exhibits an effective number of bits of 7.32 at a low sampling rate of 10 ksamples/s. The total power consumption of the chip is 26.02 μμW, which makes it highly suitable for a multi-channel neural signal recording system.
6 citations
4 citations
TL;DR: A digital‐ramp hybrid exponential‐linear analog‐to‐digital converter (ADC) is presented in this paper, which is attractive, where a high dynamic range (DR) is required.
3 citations
TL;DR: In this paper, a single loop 3rd order discrete-time Sigma-Delta modulator (Δ M ) using a single operational amplifier (Op-Amp) is presented.
Abstract: This paper presents a single loop 3rd order discrete-time Sigma–Delta Modulator ( Σ Δ M ) using a single operational amplifier (Op-Amp). The proposed Σ Δ M utilises delay-based discrete-time integrators and a single Op-Amp is used to implement all the integrators of the proposed design. The delay-based design helps in relaxing the settling time requirement of an integrator, also the error due to slewing in the output of the integrator is avoided. A switched capacitor Op-Amp based proposed design is simulated in standard 180~nm CMOS technology with a resolution of 10.75 bits. The proposed Σ Δ M achieves a signal-to-noise-distortion ratio (SNDR) of 66.48 dB and dynamic range (DR) of 70 dB. An input signal of −4 dBFS magnitude at a frequency of 2.125 kHz is sampled with a sampling frequency of 1.024 MHz. The proposed circuit is designed for a bandwidth (BW) of 20 kHz with an over-sampling-ratio (OSR) of 25.6. The proposed modulator achieves a figure-of-merit (FOMS/FOMW) of 156.48 dB/0.290 (pJ/conversion-step) with the total power consumption of 20 µW at 1.8 V supply voltage (VDD). A Monte-Carlo simulation for the SNDR of the proposed design is done and the achieved mean and standard deviation (SD) is 66.09 dB and 1.025 respectively for 1000 samples.
2 citations
References
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01 Jan 2009
TL;DR: This paper presents a meta-anatomy of Biomedical Signal Analysis, focusing on the role of ECG waves in the development of central nervous system diseases and their role in the management of disease progression.
Abstract: Dedication. Preface. About the Author. Acknowledgments. Symbols and Abbreviations. 1 Introduction to Biomedical Signals. 1.1 The Nature of Biomedical Signals. 1.2 Examples of Biomedical Signals. 1.3 Objectives of Biomedical Signal Analysis. 1.4 Difficulties in Biomedical Signal Analysis. 1.5 Computer-aided Diagnosis. 1.6 Remarks. 1.7 Study Questions and Problems. 1.8 Laboratory Exercises and Projects. 2 Concurrent, Coupled, and Correlated Processes. 2.1 Problem Statement. 2.2 Illustration of the Problem with Case-studies. 2.3 Application: Segmentation of the PCG. 2.4 Remarks. 2.5 Study Questions and Problems. 2.6 Laboratory Exercises and Projects. 3 Filtering for Removal of Artifacts. 3.1 Problem Statement. 3.2 Illustration of the Problem with Case-studies. 3.3 Time-domain Filters. 3.4 Frequency-domain Filters. 3.5 Optimal Filtering: The Wiener Filter. 3.6 Adaptive Filters for Removal of Interference. 3.7 Selecting an Appropriate Filter. 3.8 Application: Removal of Artifacts in the ECG. 3.9 Application: Maternal - Fetal ECG. 3.10 Application: Muscle-contraction Interference. 3.11 Remarks. 3.12 Study Questions and Problems. 3.13 Laboratory Exercises and Projects. 4 Event Detection. 4.1 Problem Statement. 4.2 Illustration of the Problem with Case-studies. 4.3 Detection of Events and Waves. 4.4 Correlation Analysis of EEG channels. 4.5 Cross-spectral Techniques. 4.6 The Matched Filter. 4.7 Detection of the P Wave. 4.8 Homomorphic Filtering. 4.9 Application: ECG Rhythm Analysis. 4.10 Application: Identification of Heart Sounds. 4.11 Application: Detection of the Aortic Component of S2. 4.12 Remarks. 4.13 Study Questions and Problems. 4.14 Laboratory Exercises and Projects. 5 Waveshape and Waveform Complexity. 5.1 Problem Statement. 5.2 Illustration of the Problem with Case-studies. 5.3 Analysis of Event-related Potentials. 5.4 Morphological Analysis of ECG Waves. 5.5 Envelope Extraction and Analysis. 5.6 Analysis of Activity. 5.7 Application: Normal and Ectopic ECG Beats. 5.8 Application: Analysis of Exercise ECG. 5.9 Application: Analysis of Respiration. 5.10 Application: Correlates of Muscular Contraction. 5.11 Remarks. 5.12 Study Questions and Problems. 5.13 Laboratory Exercises and Projects. 6 Frequency-domain Characterization. 6.1 Problem Statement. 6.2 Illustration of the Problem with Case-studies. 6.3 The Fourier Spectrum. 6.4 Estimation of the Power Spectral Density Function. 6.5 Measures Derived from PSDs. 6.6 Application: Evaluation of Prosthetic Valves. 6.7 Remarks. 6.8 Study Questions and Problems. 6.9 Laboratory Exercises and Projects. 7 Modeling Biomedical Systems. 7.1 Problem Statement. 7.2 Illustration of the Problem. 7.3 Point Processes. 7.4 Parametric System Modeling. 7.5 Autoregressive or All-pole Modeling. 7.6 Pole-zero Modeling. 7.7 Electromechanical Models of Signal Generation. 7.8 Application: Heart-rate Variability. 7.9 Application: Spectral Modeling and Analysis of PCG Signals. 7.10 Application: Coronary Artery Disease. 7.11 Remarks. 7.12 Study Questions and Problems. 7.13 Laboratory Exercises and Projects. 8 Analysis of Nonstationary Signals. 8.1 Problem Statement. 8.2 Illustration of the Problem with Case-studies. 8.3 Time-variant Systems. 8.4 Fixed Segmentation. 8.5 Adaptive Segmentation. 8.6 Use of Adaptive Filters for Segmentation. 8.7 Application: Adaptive Segmentation of EEG Signals. 8.8 Application: Adaptive Segmentation of PCG Signals. 8.9 Application: Time-varying Analysis of Heart-rate Variability. 8.10 Remarks. 8.11 Study Questions and Problems. 8.12 Laboratory Exercises and Projects. 9 Pattern Classification and Diagnostic Decision. 9.1 Problem Statement. 9.2 Illustration of the Problem with Case-studies. 9.3 Pattern Classification. 9.4 Supervised Pattern Classification. 9.5 Unsupervised Pattern Classification. 9.6 Probabilistic Models and Statistical Decision. 9.7 Logistic Regression Analysis. 9.8 The Training and Test Steps. 9.9 Neural Networks. 9.10 Measures of Diagnostic Accuracy and Cost. 9.11 Reliability of Classifiers and Decisions. 9.12 Application: Normal versus Ectopic ECG Beats. 9.13 Application: Detection of Knee-joint Cartilage Pathology. 9.14 Remarks. 9.15 Study Questions and Problems. 9.16 Laboratory Exercises and Projects. References. Index.
674 citations
"An adaptive continuous-time increme..." refers methods in this paper
...It has been calculated by averaging the power consumption in different window times.(27) When the adaptive ADC operates only in high‐resolution (8‐bit) mode, it has the highest‐power dissipation....
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08 May 2009
TL;DR: A 128-channel neural recording integrated circuit with on-the-fly spike feature extraction and wireless telemetry with computationally efficient spike detection and feature extraction algorithms attribute to an auspicious DSP implementation on-chip.
Abstract: This paper reports a 128-channel neural recording integrated circuit (IC) with on-the-fly spike feature extraction and wireless telemetry. The chip consists of eight 16-channel front-end recording blocks, spike detection and feature extraction digital signal processor (DSP), ultra wideband (UWB) transmitter, and on-chip bias generators. Each recording channel has amplifiers with programmable gain and bandwidth to accommodate different types of biological signals. An analog-to-digital converter (ADC) shared by 16 amplifiers through time-multiplexing results in a balanced trade-off between the power consumption and chip area. A nonlinear energy operator (NEO) based spike detector is implemented for identifying spikes, which are further processed by a digital frequency-shaping filter. The computationally efficient spike detection and feature extraction algorithms attribute to an auspicious DSP implementation on-chip. UWB telemetry is designed to wirelessly transfer raw data from 128 recording channels at a data rate of 90 Mbit/s. The chip is realized in 0.35 mum complementary metal-oxide-semiconductor (CMOS) process with an area of 8.8 times 7.2 mm2 and consumes 6 mW by employing a sequential turn-on architecture that selectively powers off idle analog circuit blocks. The chip has been tested for electrical specifications and verified in an ex vivo biological environment.
377 citations
"An adaptive continuous-time increme..." refers background in this paper
...The number of the utilized ADCs is equal to the number of recording channels(1) or several ADCs are shared between all channels to minimize the chip area.(3,4) However, the SAR ADC has stringent requirements in the reference buffer and front‐end circuits resulting in more power consumption....
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TL;DR: It is shown how speed, resolution, and A/D complexity can be optimized for a given design, and how with some special digital filters improved speed/resolution ratio can be achieved.
Abstract: Analog-Digital (A/D) converters used in instrumentation and measurements often require high absolute accuracy, including very high linearity and negligible dc offset. The realization of high-resolution Nyquist-rate converters becomes very expensive when the resolution exceeds 16 bits. The conventional delta-sigma (/spl Delta//spl Sigma/) structures used in telecommunication and audio applications usually cannot satisfy the requirements of high absolute accuracy and very small offset. The incremental (or integrating) converter provides a solution for such measurement applications, as it has most advantages of the /spl Delta//spl Sigma/ converter, yet is capable of offset-free and accurate conversion. In this paper, theoretical and practical aspects of higher order incremental converters are discussed. The operating principles, topologies, specialized digital filter design methods, and circuit level issues are all addressed. It is shown how speed, resolution, and A/D complexity can be optimized for a given design, and how with some special digital filters improved speed/resolution ratio can be achieved. The theoretical results are verified by showing design examples and simulation results.
269 citations
21 Mar 2006-Journal of Comparative Physiology A-neuroethology Sensory Neural and Behavioral Physiology
TL;DR: Experimental findings pointing to the existence of neurons which fire action potentials rarely or only to very specific stimuli are reviewed, in order to discuss the evidence for largely silent neurons.
Abstract: Evidence from a variety of recording methods suggests that many areas of the brain are far more sparsely active than commonly thought. Here, we review experimental findings pointing to the existence of neurons which fire action potentials rarely or only to very specific stimuli. Because such neurons would be difficult to detect with the most common method of monitoring neural activity in vivo—extracellular electrode recording—they could be referred to as “dark neurons,” in analogy to the astrophysical observation that much of the matter in the universe is undetectable, or dark. In addition to discussing the evidence for largely silent neurons, we review technical advances that will ultimately answer the question: how silent is the brain?
247 citations
"An adaptive continuous-time increme..." refers result in this paper
...It is worth mentioning that this previously recorded neural signal has the same average number of APs as in other study.(15) Figure 17 shows the simulated transient response of the adaptive ADC....
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TL;DR: An implantable microsystem capable of recording neural activity simultaneously on 64 channels, wirelessly transmitting spike occurrences to an external interface, and allows the user to examine the spike waveforms on any channel with 8 bit resolution is reported.
Abstract: This paper reports an implantable microsystem capable of recording neural activity simultaneously on 64 channels, wirelessly transmitting spike occurrences to an external interface. The microsystem also allows the user to examine the spike waveforms on any channel with 8 bit resolution. Signals are amplified by 60 dB with a programmable bandwidth from < 100 Hz to 10 kHz. The input-referred noise is 8 ?Vrms. The channel scan rate for spike detection is 62.5 kS/sec using a 2 MHz clock. The system dissipates 14.4 mW at 1.8 V, weighs 275 mg, and measures 1.4 cm 1.55 cm.
233 citations