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Proceedings ArticleDOI

An algorithm for finding a non-trivial lower bound for channel routing

04 Jan 1997-pp 531-532

AbstractChannel routing is a key problem in the physical design of VLSI chips. It is known that max(d/sub max,/v/sub max/) is a lower bound on the number of tracks required in the reserved two-layer Manhattan routing model, where d/sub max/ is the channel density and v/sub max/ is the length of the longest path in the vertical constraint graph. In this paper we propose a polynomial time algorithm that computes a better and non-trivial lower bound on the number of trades required for routing a channel without doglegging. This algorithm is also applicable for computing a lower bound on the number of tracks in the three-layer no-dogleg HVH routing as well as two- and three-layer restricted dogleg routing models.

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Citations
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Proceedings ArticleDOI
21 Feb 2013
TL;DR: This work proposes a new algorithm to reduce the number of tracks using four layers (two horizontal layers and two vertical layers) and converts a two-layer channel routing problem into a four-layerChannel routing problem using HNCG and VCG of the channel.
Abstract: Channel routing is a key problem in VLSI physical design. The main goal of the channel routing problem is to reduce the area of an IC chip. If we concentrate on reducing track number in channel routing problem then automatically the area of an IC chip will be reduced. Here, we propose a new algorithm to reduce the number of tracks using four layers (two horizontal layers and two vertical layers). To be more specific, through this algorithm we convert a two-layer channel routing problem into a four-layer channel routing problem using HNCG and VCG of the channel. Next, we show the experimental results and graphical structure of that solution.

3 citations

Journal ArticleDOI
TL;DR: This paper analyzes The Efficient Routing algorithm and resolve horizontal constraints and minimize the net wirelength in a particular model of channel routing using MCC1 and MCC2 algorithms.
Abstract: We know that channel routing is very important problem in VLSI physical design. The main objective of a channel routing algorithm is the reduction of the area of a IC chip. In this paper, we just do a survey on some impotent multi-layer routing algorithms. Here we analyze The Efficient Routing algorithm and resolve horizontal constraints and minimize the net wirelength in a particular model of channel routing using MCC1 and MCC2 algorithms. Next, we analyze an algorithm for Multi channel Routing MulCh and its differences from Chameleon which s another multi channel routing in the two-layer VH and three-layer HVH routing models.

1 citations

Proceedings ArticleDOI
01 Dec 2011
TL;DR: This paper considers a general channel routing problem for channel instances with fixed and floating terminals, and develops an efficient graph based heuristic algorithm for reducing area in the reserved two-layer Manhattan channel routing model.
Abstract: The main objective of VLSI channel routing problem is to compute a feasible reduced area routing solution which reduces the height of the channel. A channel is a rectangular routing region with two open ends (left and right) and two sets of fixed terminals (top terminals and bottom terminals) are placed in the upper and lower sides of the channel. A net is a set of terminals that need to be electrically connected (usually using rectilinear wiring). Routing is a process to interconnect all nets within the channel considering all constraints (horizontal and vertical constraints) of that channel. The terminals along the left and right ends of the channel are not fixed, known as floating terminals. Generally, channel routing problem for area minimization is NP-complete. So developing a heuristic algorithm is really interesting. In this paper, we consider a general channel routing problem for channel instances with fixed and floating terminals, and develop an efficient graph based heuristic algorithm for reducing area in the reserved two-layer Manhattan channel routing model.
Journal ArticleDOI
31 Oct 2012
TL;DR: This work proposes a new algorithm to reduce the number of tracks using four layers (two horizontal layers and two vertical layers) of the channel and shows the experimental results and graphical structure of that solution.
Abstract: Channel routing is a key problem in VLSI physical design. The main goal of the channel routing problem is to reduce the area of an IC chip. If we concentrate on reducing track number in channel routing problem then automatically the area of an IC chip will be reduced. Here, we propose a new algorithm to reduce the number of tracks using four layers (two horizontal layers and two vertical layers). To be more specific, through this algorithm we convert a two-layer channel routing problem into a four-layer channel routing problem using VCG of the channel. Next, we show the experimental results and graphical structure of that solution.

References
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Book
01 Jan 1980
TL;DR: This new Annals edition continues to convey the message that intersection graph models are a necessary and important tool for solving real-world problems and remains a stepping stone from which the reader may embark on one of many fascinating research trails.
Abstract: Algorithmic Graph Theory and Perfect Graphs, first published in 1980, has become the classic introduction to the field. This new Annals edition continues to convey the message that intersection graph models are a necessary and important tool for solving real-world problems. It remains a stepping stone from which the reader may embark on one of many fascinating research trails. The past twenty years have been an amazingly fruitful period of research in algorithmic graph theory and structured families of graphs. Especially important have been the theory and applications of new intersection graph models such as generalizations of permutation graphs and interval graphs. These have lead to new families of perfect graphs and many algorithmic results. These are surveyed in the new Epilogue chapter in this second edition. New edition of the "Classic" book on the topic Wonderful introduction to a rich research area Leading author in the field of algorithmic graph theory Beautifully written for the new mathematician or computer scientist Comprehensive treatment

4,086 citations

Journal ArticleDOI
TL;DR: Two new algorithms merge nets instead of assigning horizontal tracks to individual nets to route a specified net list between two rows of terminals across a two-layer channel in the layout design of LSI chips.
Abstract: In the layout design of LSI chips, channel routing is one of the key problems. The problem is to route a specified net list between two rows of terminals across a two-layer channel. Nets are routed with horizontal segments on one layer and vertical segments on the other. Connections between two layers are made through via holes. Two new algorithms are proposed. These algorithms merge nets instead of assigning horizontal tracks to individual nets. The algorithms were coded in Fortran and implemented on a VAX 11/780 computer. Experimental results are quite encouraging. Both programs generated optimal solutions in 6 out of 8 cases, using examples in previously published papers. The computation times of the algorithms for a typical channel (300 terminals, 70 nets) are 1.0 and 2.1 s, respectively.

538 citations

Journal ArticleDOI
T.G. Szymanski1
TL;DR: It is shown that an efficient optimal algorithm for interconnecting two rows of points across an intervening channel is unlikely to exist by establishing that this problem is NP-complete.
Abstract: Interconnecting two rows of points across an intervening channel is an important problem in the design of LSI circuits. The most common methodology for producing such interconnections uses two orthogonal layers of parallel conductors and allows wires to "dogleg" arbitrarily. Although effective heuristic procedures are available for routing channels with this methodology, no efficient optimal algorithm has yet been discovered for the general case problem. We show that such an algorithm is unlikely to exist by establishing that this problem is NP-complete.

206 citations

01 Nov 1980
TL;DR: The major result presented in this dissertation is a polynomial time algorithm for a restricted case of the routing problem, which minimizes the area of a rectangle circumscribing the component and the wire paths.
Abstract: In this thesis, the problem of designing the layout of integrated circuits is examined. The layout of an integrated circuit specifies the position of the chip of functional components and wires interconnecting the components. We use a general model under which components are represented by rectangles, and wires are represented by lines. This model can be applied to circuit components defined at any level of complexity, from a transistor to a programmable logic array (PLA). We focus on the standard decomposition of the layout problem into a placement problem and a routing problem. We examine problems encountered in layout design from the point of view of complexity theory. The general layout problem under our model is shown to be NP-complete. In addition, two problems encountered in a restricted version of the routing problem --channel routing--are shown to be NP-complete. The analysis of heuristic algorithms for NP-complete problems is discussed, and the analysis of one common algorithm is presented. The major result presented in this dissertation is a polynomial time algorithm for a restricted case of the routing problem. Given one rectangular component with terminals on its boundary, and pairs of terminals to be connected, the algorithm will find a two-layer channel routing which minimizes the area of a rectangle circumscribing the component and the wire paths. Each terminal can appear in only one pair of terminals to be connected, and the rectangle used to determine the area must have its boundaries parallel to those of the component. If any of the conditions of the problem are removed, the algorithm is no longer guaranteed to find the optimal solution.

83 citations

01 Jan 1989

18 citations