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Journal ArticleDOI

An algorithm for finding a non-trivial lower bound for channel routing

01 Sep 1998-Integration (Elsevier)-Vol. 25, Iss: 1, pp 71-84

TL;DR: A deterministic polynomial time algorithm is proposed that computes a better and non-trivial lower bound on the number of tracks required for routing a channel without doglegging.

AbstractChannel routing is a key problem in the physical design of VLSI chips. It is known that max(d max , v max ) is a lower bound on the number of tracks required in the reserved two-layer Manhattan routing model, where dmax is the channel density and vmax is the length of the longest path in the vertical constraint graph. In this paper we propose a deterministic polynomial time algorithm that computes a better and non-trivial lower bound on the number of tracks required for routing a channel without doglegging. This algorithm is also applicable for computing a lower bound on the number of tracks in the three-layer no-dogleg HVH routing as well as two- and three-layer restricted dogleg routing models.

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Citations
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Journal Article
TL;DR: This paper visualize the two important constraints present in a channel, horizontal constraint and vertical constraint, through graphs in a different way, and combinedly use them to compute reduced area channel routing solutions.
Abstract: Channel routing problem is a problem in VLSI physical design whose objective is to compute a feasible minimum area routing solution. A channel is a rectangular routing region where the terminals are usually present on two of its opposite sides, and the other two sides are open ends. Routing is the task to interconnect all the nets present in a channel obeying constraints within the channel region. A net is a set of terminals that need to be electrically connected (usually using rectilinear wiring). The two important constraints present in a channel are horizontal constraint and vertical constraint. In this paper we visualize these two constraints through graphs in a different way, and combinedly use them to compute reduced area channel routing solutions.

5 citations

Proceedings ArticleDOI
04 Jan 1997
Abstract: Channel routing is a key problem in the physical design of VLSI chips. It is known that max(d/sub max,/v/sub max/) is a lower bound on the number of tracks required in the reserved two-layer Manhattan routing model, where d/sub max/ is the channel density and v/sub max/ is the length of the longest path in the vertical constraint graph. In this paper we propose a polynomial time algorithm that computes a better and non-trivial lower bound on the number of trades required for routing a channel without doglegging. This algorithm is also applicable for computing a lower bound on the number of tracks in the three-layer no-dogleg HVH routing as well as two- and three-layer restricted dogleg routing models.

4 citations

Proceedings ArticleDOI
21 Feb 2013
TL;DR: This work proposes a new algorithm to reduce the number of tracks using four layers (two horizontal layers and two vertical layers) and converts a two-layer channel routing problem into a four-layerChannel routing problem using HNCG and VCG of the channel.
Abstract: Channel routing is a key problem in VLSI physical design. The main goal of the channel routing problem is to reduce the area of an IC chip. If we concentrate on reducing track number in channel routing problem then automatically the area of an IC chip will be reduced. Here, we propose a new algorithm to reduce the number of tracks using four layers (two horizontal layers and two vertical layers). To be more specific, through this algorithm we convert a two-layer channel routing problem into a four-layer channel routing problem using HNCG and VCG of the channel. Next, we show the experimental results and graphical structure of that solution.

3 citations

01 Jan 2007
TL;DR: This paper has a definite refinement of lower bound on the number of tracks required to route a channel and performs exact mapping of the problem into graphical presentation and analyzes the graph taking help of mimetic algorithm, which uses combination of sequential and GA based vertex coloring.
Abstract: Study of algorithms and its design can be progressed in various dimensions. In this paper, we have a definite refinement of lower bound on the number of tracks required to route a channel. The attack is from a complementary viewpoint. Our algorithm succeeds to avoid all kinds of approximation. The approach performs exact mapping of the problem into graphical presentation and analyzes the graph taking help of mimetic algorithm, which uses combination of sequential and GA based vertex coloring. Performance of the algorithm depends on how effectively mimetic approach can be applied selecting appropriate values for the parameters to evaluate the graphical presentation of the problem. This viewpoint has immense contribution against sticking at local minima for this optimization problem. The finer result clearly exemplifies instances, which give better or at least the same lower bound in VLSI channel routing problem.

2 citations


Cites background or methods from "An algorithm for finding a non-triv..."

  • ...This paper emphasizes on finding a better nontrivial lower bound than the earlier deterministic algorithm [9]....

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  • ...Theorem 1: MIMETIC_LBOUND computes exact lower bound on the number of track requirement to route a channel, and result is better or at least equal to that found using LOWER_BOUND algorithm [9]....

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  • ...Channel instance dmax vmax max(dmax, vmax) Lbound by our algorithm CPU time Best solution known [9] CH1 4 4 4 6 0....

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  • ...The deterministic version of computing a nontrivial lower bound is presented in [9], that took time Ο(n) for a channel of n nets....

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  • ...MIMETIC_LBOUND also provides result as good as earlier computed lower bound for Deutsch’s difficult example (DDE) [9]....

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Journal ArticleDOI
TL;DR: This paper analyzes The Efficient Routing algorithm and resolve horizontal constraints and minimize the net wirelength in a particular model of channel routing using MCC1 and MCC2 algorithms.
Abstract: We know that channel routing is very important problem in VLSI physical design. The main objective of a channel routing algorithm is the reduction of the area of a IC chip. In this paper, we just do a survey on some impotent multi-layer routing algorithms. Here we analyze The Efficient Routing algorithm and resolve horizontal constraints and minimize the net wirelength in a particular model of channel routing using MCC1 and MCC2 algorithms. Next, we analyze an algorithm for Multi channel Routing MulCh and its differences from Chameleon which s another multi channel routing in the two-layer VH and three-layer HVH routing models.

1 citations


References
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Book
01 Jan 1980
TL;DR: This new Annals edition continues to convey the message that intersection graph models are a necessary and important tool for solving real-world problems and remains a stepping stone from which the reader may embark on one of many fascinating research trails.
Abstract: Algorithmic Graph Theory and Perfect Graphs, first published in 1980, has become the classic introduction to the field. This new Annals edition continues to convey the message that intersection graph models are a necessary and important tool for solving real-world problems. It remains a stepping stone from which the reader may embark on one of many fascinating research trails. The past twenty years have been an amazingly fruitful period of research in algorithmic graph theory and structured families of graphs. Especially important have been the theory and applications of new intersection graph models such as generalizations of permutation graphs and interval graphs. These have lead to new families of perfect graphs and many algorithmic results. These are surveyed in the new Epilogue chapter in this second edition. New edition of the "Classic" book on the topic Wonderful introduction to a rich research area Leading author in the field of algorithmic graph theory Beautifully written for the new mathematician or computer scientist Comprehensive treatment

4,086 citations

Proceedings ArticleDOI
28 Jun 1971
TL;DR: The purpose of this paper is to introduce a new wire routing method for two layer printed circuit boards based on the newly developed channel assignment algorithm and requires many via holes.
Abstract: The purpose of this paper is to introduce a new wire routing method for two layer printed circuit boards. This technique has been developed at the University of Illinois Center for Advanced Computation and has been programmed in ALGOL for a B5500 computer. The routing method is based on the newly developed channel assignment algorithm and requires many via holes. The primary goals of the method are short execution time and high wireability. Actual design specifications for ILLIAC IV Control Unit boards have been used to test the feasibility of the routing technique. Tests have shown that this algorithm is very fast and can handle large boards.

650 citations

Journal ArticleDOI
TL;DR: Two new algorithms merge nets instead of assigning horizontal tracks to individual nets to route a specified net list between two rows of terminals across a two-layer channel in the layout design of LSI chips.
Abstract: In the layout design of LSI chips, channel routing is one of the key problems. The problem is to route a specified net list between two rows of terminals across a two-layer channel. Nets are routed with horizontal segments on one layer and vertical segments on the other. Connections between two layers are made through via holes. Two new algorithms are proposed. These algorithms merge nets instead of assigning horizontal tracks to individual nets. The algorithms were coded in Fortran and implemented on a VAX 11/780 computer. Experimental results are quite encouraging. Both programs generated optimal solutions in 6 out of 8 cases, using examples in previously published papers. The computation times of the algorithms for a typical channel (300 terminals, 70 nets) are 1.0 and 2.1 s, respectively.

538 citations

Journal ArticleDOI
T.G. Szymanski1
TL;DR: It is shown that an efficient optimal algorithm for interconnecting two rows of points across an intervening channel is unlikely to exist by establishing that this problem is NP-complete.
Abstract: Interconnecting two rows of points across an intervening channel is an important problem in the design of LSI circuits. The most common methodology for producing such interconnections uses two orthogonal layers of parallel conductors and allows wires to "dogleg" arbitrarily. Although effective heuristic procedures are available for routing channels with this methodology, no efficient optimal algorithm has yet been discovered for the general case problem. We show that such an algorithm is unlikely to exist by establishing that this problem is NP-complete.

206 citations

Journal ArticleDOI
TL;DR: Two special types of three-layer channel routing, VHV and HVH, are introduced in this paper, and the merging algorithm and the left edge algorithm used in two-layer routing can be extended to three layers.
Abstract: With the advent of VLSI technology, multiple-layer routing becomes feasible. Two special types of three-layer channel routing, VHV and HVH, are introduced in this paper. The merging algorithm and the left edge algorithm used in two-layer routing can be extended to three layers. Attempts are made to compare the lower bounds of channel width of three types of routing--two-layer, VHV, and HVH. The algorithms were coded in PASCAL and implemented on VAX 11/780 computer. The computational results are satisfactory, since all the results lead to a further reduction in routing area.

104 citations