An Analog Neural Network Computing Engine Using CMOS-Compatible Charge-Trap-Transistor (CTT)
01 Oct 2019-IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (Institute of Electrical and Electronics Engineers Inc.)-Vol. 38, Iss: 10, pp 1811-1819
TL;DR: An analog neural network computing engine based on CMOS-compatible charge-trap transistor (CTT) is proposed and obtained a performance comparable to state-of-the-art fully connected neural networks using 8-bit fixed-point resolution.
Abstract: An analog neural network computing engine based on CMOS-compatible charge-trap transistor (CTT) is proposed in this paper. CTT devices are used as analog multipliers. Compared to digital multipliers, CTT-based analog multiplier shows significant area and power reduction. The proposed computing engine is composed of a scalable CTT multiplier array and energy efficient analog–digital interfaces. By implementing the sequential analog fabric, the engine’s mixed-signal interfaces are simplified and hardware overhead remains constant regardless of the size of the array. A proof-of-concept 784 by 784 CTT computing engine is implemented using TSMC 28-nm CMOS technology and occupies 0.68 mm2. The simulated performance achieves 76.8 TOPS (8-bit) with 500 MHz clock frequency and consumes 14.8 mW. As an example, we utilize this computing engine to address a classic pattern recognition problem—classifying handwritten digits on MNIST database and obtained a performance comparable to state-of-the-art fully connected neural networks using 8-bit fixed-point resolution.
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TL;DR: In this article , a multifunctional infrared image sensor based on an array of black phosphorous programmable phototransistors (bP-PPT) is presented, which can receive optical images transmitted over a broad spectral range in the infrared and perform inference computation to process and recognize the images with 92% accuracy.
Abstract: Image sensors with internal computing capability enable in-sensor computing that can significantly reduce the communication latency and power consumption for machine vision in distributed systems and robotics. Two-dimensional semiconductors have many advantages in realizing such intelligent vision sensors because of their tunable electrical and optical properties and amenability for heterogeneous integration. Here, we report a multifunctional infrared image sensor based on an array of black phosphorous programmable phototransistors (bP-PPT). By controlling the stored charges in the gate dielectric layers electrically and optically, the bP-PPT's electrical conductance and photoresponsivity can be locally or remotely programmed with 5-bit precision to implement an in-sensor convolutional neural network (CNN). The sensor array can receive optical images transmitted over a broad spectral range in the infrared and perform inference computation to process and recognize the images with 92% accuracy. The demonstrated bP image sensor array can be scaled up to build a more complex vision-sensory neural network, which will find many promising applications for distributed and remote multispectral sensing.
32 citations
Posted Content•
TL;DR: In this article, a multispectral infrared image sensor based on an array of black phosphorous programmable phototransistors (bP-PPT) is presented.
Abstract: Image sensors with internal computing capability enable in-sensor computing that can significantly reduce the communication latency and power consumption for machine vision in distributed systems and robotics. Two-dimensional semiconductors are uniquely advantageous in realizing such intelligent visionary sensors because of their tunable electrical and optical properties and amenability for heterogeneous integration. Here, we report a multifunctional infrared image sensor based on an array of black phosphorous programmable phototransistors (bP-PPT). By controlling the stored charges in the gate dielectric layers electrically and optically, the bP-PPT's electrical conductance and photoresponsivity can be locally or remotely programmed with high precision to implement an in-sensor convolutional neural network (CNN). The sensor array can receive optical images transmitted over a broad spectral range in the infrared and perform inference computation to process and recognize the images with 92% accuracy. The demonstrated multispectral infrared imaging and in-sensor computing with the black phosphorous optoelectronic sensor array can be scaled up to build a more complex visionary neural network, which will find many promising applications for distributed and remote multispectral sensing.
32 citations
TL;DR: In this article, the authors present the three-terminal synaptic devices based on ferroelectric field effect transistor (FeFET), and discuss the switching physics of the intermediate states, the back-end-of-line (BEOL) integration and the 3D NAND architecture design.
Abstract: Neuro-inspired deep learning algorithm has shown promising futures for artificial intelligence (AI). Despite the remarkable progress on software-based neural network, the traditional von-Neumann hardware architecture has suffered from limited energy efficiency while facing unprecedented large amount of data. In order to meet the performance requirement of neuro-inspired computing, the large-scale vector-matrix multiplication is preferred to be performed in-situ, namely compute-in-memory (CIM). Non-volatile memory devices with different materials have been proposed for weight storage as synaptic devices. Among them, the HfO2-based ferroelectric devices have obtained great attention because of their low energy consumption, good CMOS compatibility and multi-bit per cell potential. In this review, recent trends and prospects of the ferroelectric synaptic devices are surveyed. First, we present the three-terminal synaptic devices based on ferroelectric field effect transistor (FeFET), and discuss the switching physics of the intermediate states, the back-end-of-line (BEOL) integration and the 3D NAND architecture design. Then, we introduce hybrid precision synapse concept that leverages the volatile charges on the gate capacitor of FeFET and the non-volatile polarization on the gate dielectric of FeFET. Lastly, we review two-terminal synaptic devices using ferroelectric tunnel junction (FTJ) and ferroelectric capacitor (FeCAP). Design margins of the crossbar array with FTJ and FeCAP are analyzed.
18 citations
TL;DR: A comprehensive investigation of the programming behavior of CTTs, including analog retention, intra- and inter-device variation, and fine-tuning of the device, both for individual devices and for devices in an integrated array reveals the promising future of using the CTT as a CMOS-only analog memory device.
Abstract: Since our demonstration of unsupervised learning using the CMOS-only charge-trap transistors (CTTs) as analog synapses, there has been an increasing interest in exploiting the device for various other neural network (NN) applications. However, most of these studies are limited to mere simulation due to the absence of detailed experimental device characterization. In this article, we provide a comprehensive investigation of the programming behavior of CTTs, including analog retention, intra- and inter-device variation, and fine-tuning of the device, both for individual devices and for devices in an integrated array. It is found that, after programming, the channel current gradually increases to a higher level, and the shift is larger when the device is programmed to a higher threshold voltage. With this postprogramming current increase appropriately accounted for, individual devices can be programmed to an equivalent precision of five bits, and three bits can be achieved for devices in an array. Our results reveal the promising future of using the CTT as a CMOS-only analog memory device.
18 citations
Cites methods from "An Analog Neural Network Computing ..."
...For example, in [34], an analog inference engine using the CTT as the analog synapses was proposed, and the simulation shows significant performance edge over conventional digital approaches....
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07 Sep 2020
TL;DR: The recent trends of IMC from techniques (SRAM, flash, RRAM and other types of non-volatile memory) to architecture and to applications are investigated to serve as a guide to the future advances on computing in-memory (CIM).
Abstract: To overcome the memory bottleneck of von-Neuman architecture, various memory-centric computing techniques are emerging to reduce the latency and energy consumption caused by data communication. The great success of artificial intelligence (AI) algorithms, which involve a large number of computations and data movements, has motivated and accelerated the recent researches of in-memory computing (IMC) techniques to significantly reduce or even diminish the accesses of off-chip data, where memory is not only storing data but can also directly output computation results. For example, the multiply-and-accumulate (MAC) operations in deep learning algorithms can be realized by accessing the memory using the input activations. This paper will investigate the recent trends of IMC from techniques (SRAM, flash, RRAM and other types of non-volatile memory) to architecture and to applications, which will serve as a guide to the future advances on computing in-memory (CIM).
11 citations
Cites background or methods from "An Analog Neural Network Computing ..."
...We then survey recent computingin-memory research based on different types of NVM devices, including Flash memory, ReRAM, STT-MRAM, PCM, and the emerging non-volatile devices [38]....
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...KEYWORDS In-memory computing (IMC), SRAM, NVM, deep learning, convolutional neural networks (CNNs), ACM Reference format: Yufei Ma, Yuan Du, Li Du, Jun Lin and Zhongfeng Wang....
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...Ref [22] Ref [23] Ref [38] Ref [25] Ref [26] Ref [34] Ref [30]...
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