Proceedings ArticleDOI
An analysis of power supply induced jitter for a voltage mode driver in high speed serial links
Jai Narayan Tripathi,Vijender Kumar Sharma,Hiten Advani,Pratap Narayan Singh,Hitesh Shrimali,Rakesh Malik +5 more
- pp 1-4
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TLDR
In this paper, an analysis of power supply induced jitter in a commonly used voltage mode driver architecture in serial links is discussed, and the analysis can be extended generically for System-On-Chip (SoC) level design considerations.Abstract:
Estimation of jitter in early design cycle of an SoC is necessary to avoid jitter budget conflicts in the design. In this paper, an analysis of power supply induced jitter in a commonly used voltage mode driver architecture in serial links is discussed. The circuit used for the analysis is designed in 28nm FD-SOI technology but the analysis is technology independent. Jitter induced by noise in power delivery networks is analyzed by a transfer function from power supply to the output by a small signal equivalent model. The analysis can be extended generically for System-On-Chip (SoC) level design considerations.read more
Citations
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Journal ArticleDOI
A Review on Power Supply Induced Jitter
TL;DR: The primary focus of this paper is to discuss the modeling of jitter caused by power supply noise (PSN), named power supply induced jitter (PSIJ).
Journal ArticleDOI
Efficient Modeling of Power Supply Induced Jitter in Voltage-Mode Drivers (EMPSIJ)
TL;DR: In this paper, an efficient methodology for estimation of power supply induced jitter (PSIJ) in high-speed designs is presented, based on separating the large signal response and the small signal noise response and subsequently combining the results.
Journal ArticleDOI
Fast Analysis of Time Interval Error in Current-Mode Drivers
TL;DR: An efficient approach for modeling of time interval error (TIE) due to noise in power delivery networks (PDNs), for current-mode (CM) driver circuits, is presented and a significant speedup is demonstrated using the proposed approach.
Journal ArticleDOI
An Efficient Estimation of Power Supply-Induced Jitter by Numerical Method
TL;DR: This letter presents an efficient and generic methodology for the estimation of power supply-induced jitter by the numerical method using a root-finding approach and reports a significant speed-up reported compared with the simulations by a commercial simulator.
Journal ArticleDOI
A Thomas Algorithm-Based Generic Approach for Modeling of Power Supply Induced Jitter in CMOS Buffers
TL;DR: An efficient and generic method for analysis of power supply induced jitter (PSIJ) in a chain of CMOS inverters as well as tapered buffers due to multiple deterministic noise sources is presented.
References
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Book
Power Integrity Modeling and Design for Semiconductors and Systems
Madhavan Swaminathan,A.E. Engin +1 more
TL;DR: This book's system-level focus and practical examples will make it indispensable for every student and professional concerned with power integrity, including electrical engineers, system designers, signal integrity engineers, and materials scientists.
Book
Jitter, Noise, and Signal Integrity at High-Speed
TL;DR: The fundamental terminology, definitions, and concepts associated with JNB and SI, as well as their sources and root causes are introduced, and Dr. Li provides powerful new tools for solving these problems quickly, efficiently, and reliably.
Proceedings ArticleDOI
Analytical expressions for transfer function of supply voltage fluctuation to jitter at a single-ended buffer
TL;DR: The transfer function of a supply voltage fluctuation to jitter is analytically solved for a single ended buffer in closed-form expressions and validated by comparison with HSPICE simulation.
Proceedings ArticleDOI
The combined effect of process variations and power supply noise on clock skew and jitter
TL;DR: In modern VLSI circuits, a large number of clock buffers are inserted in clock distribution networks, which are significantly affected by process and power supply noise variations, and a statistical model of skitter, which consists of skew and jitter is proposed.
Proceedings ArticleDOI
Impact of Power Supply Noise on Clock Jitter in High-Speed DDR Memory Interfaces
TL;DR: This paper presents methods that have been used at the architectural and system levels and in physical design to alleviate the effect of the supply noise on the DDR clock.