An Analytical Approach to Direct IP Protection of VLSI Floorplans
01 Dec 2008-pp 1-6
TL;DR: Encoding moves for various floorplan representations are analyzed in terms of their time and space requirements and experimental results on MCNC benchmarks are encouraging.
Abstract: In the DSM VLSI technology, wide-spread design reuse to meet customer's requirements in time enhances the probability of infringement of intellectual property (IP) of VLSI physical design. In design storage or during design transmission between two parties, encryption of a design file is a well-known technique to protect a design against hacking, although it takes significantly long time to encrypt large design files. While encryption basically substitutes and shuffles the bits/ASCII values of a file to conceal the contents of the file, the IP value of a design obtained from optimized partitioning, floorplanning and placement can be protected by redistribution of design elements in the modules and exchanging the locations and orientations of the design modules. As security of design through perturbation exploits the basic properties of physical design, this technique is applicable to protect any intermediate phase, not restricted to binary/ASCII GDSII/OASIS file format only. In this paper, encoding moves for various floorplan representations are analyzed in terms of their time and space requirements. Experimental results on MCNC benchmarks are encouraging.
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05 Jan 2009
TL;DR: The idea of an alternate efficient approach of encoding by deterministic perturbation of design IP resulting in a degraded design of negligible IP value, is proposed here to ensure security during design storage or transmission.
Abstract: Recent trends in VLSI design involve rapid growth of design reuse and electronic Intellectual Property (IP) commerce. For VLSI physical design, the risk of misappropriation of design IP stored in design repositories, or the threat of hacking the same during its web-based transmission, mandates design file encryption. However, encryption of GDSII/OASIS design files, too large in size and complex in format, is troublesome, time consuming and also prone to typical cryptanalysis. The idea of an alternate efficient approach of encoding by deterministic perturbation of design IP resulting in a degraded design of negligible IP value, is proposed here to ensure security during design storage or transmission. From the highly degraded design only authorized person can quickly regenerate the optimized design. In this paper, the technique for design encoding through perturbation is applied for floorplanning stage. Encoding moves for various floorplan representations are analyzed and a novel technique for encoding tree-based representations is proposed. Experimental results on floorplan perturbation for MCNC benchmarks are encouraging.
4 citations
Cites background or result from "An Analytical Approach to Direct IP..."
...In [3] and [11], some preliminary techniques for design perturbation are addressed....
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...This degradation is more compared to that in [11]....
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Book•
01 Jan 1996TL;DR: A valuable reference for the novice as well as for the expert who needs a wider scope of coverage within the area of cryptography, this book provides easy and rapid access of information and includes more than 200 algorithms and protocols.
Abstract: From the Publisher:
A valuable reference for the novice as well as for the expert who needs a wider scope of coverage within the area of cryptography, this book provides easy and rapid access of information and includes more than 200 algorithms and protocols; more than 200 tables and figures; more than 1,000 numbered definitions, facts, examples, notes, and remarks; and over 1,250 significant references, including brief comments on each paper.
13,597 citations
"An Analytical Approach to Direct IP..." refers background or methods in this paper
...K is encrypted [15] using public key encryption, RSA and transmitted through ultra-secure channel between these two parties....
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...interception of one copy of the design file with the original file kept unaltered [15]....
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TL;DR: This paper attacks the biggest MCNC benchmark ami49 with a conventional wiring area estimation method, and obtain a highly promising placement, and proposes a solution space where each packing is represented by a pair of module name sequences, called a sequence-pair.
Abstract: The earliest and the most critical stage in VLSI layout design is the placement. The background is the rectangle packing problem: given a set of rectangular modules of arbitrary sizes, place them without overlap on a plane within a rectangle of minimum area. Since the variety of the packing is uncountably infinite, the key issue for successful optimization is the introduction of a finite solution space which includes an optimal solution. This paper proposes such a solution space where each packing is represented by a pair of module name sequences, called a sequence-pair. Searching this space by simulated annealing, hundreds of modules have been packed efficiently as demonstrated. For applications to VLSI layout, we attack the biggest MCNC benchmark ami49 with a conventional wiring area estimation method, and obtain a highly promising placement.
687 citations
01 Jun 2000
TL;DR: An efficient, flexible, and effective data structure, B-trees for non-slicing floorplans, based on ordered binary trees and the admissible placement presented in [1], and a B-tree based simulated annealing scheme for floorplan design.
Abstract: We present in this paper an efficient, flexible, and effective data structure, B*-trees for non-slicing floorplans. B*-trees are based on ordered binary trees and the admissible placement presented in [1]. Inheriting from the nice properties of ordered binary trees, B*-trees are very easy for implementation and can perform the respective primitive tree, operations search, insertion, and deletion in only O(1), O(1), and O(n) times while existing representations for non-slicing floorplans need at least O(n) time for each of these operations, where n is the number of modules. The correspondence between an admissible placement and its induced B*-tree is 1-to-1 (i.e., no redundancy); further, the transformation between them takes only linear time. Unlike other representations for non-slicing floorplans that need to construct constraint graphs for cost evaluation, in particular, the evaluation can be performed on B*-trees and their corresponding placements directly and incrementally. We further show the flexibility of B*-trees by exploring how to handle rotated, pre-placed, soft, and rectilinear modules. Experimental results on MCNC benchmarks show that the B*-tree representation runs about 4.5 times faster, consumes about 60% less memory, and results in smaller silicon area than the O-tree one [1]. We also develop a B*-tree based simulated annealing scheme for floorplan design; the scheme achieves near optimum area utilization even for rectilinear modules.
506 citations
01 Jun 1999
TL;DR: A deterministic floorplanning algorithm utilizing the structure of O-tree is developed with promising performance with average 16% improvement in wire length, and 1% less in dead space over previous CPU-intensive cluster refinement method.
Abstract: We present an ordered tree, O-tree, structure to represent non-slicing floorplans. The O-tree uses only n(2+[Ig n]) bits for a floorplan of n rectangular blocks. We define an admissible placement as a compacted placement in both x and y direction. For each admissible placement, we can find an O-tree representation. We show that the number of possible O-tree combinations is O(n! 2/sup 2n-2//n/sup 1.5/). This is very concise compared to a sequence pair representation which has O((n!)2) combinations. The approximate ratio of sequence pair and O-tree combinations is O(n/sup 2/(n/4e)/sup n/). The complexity of the O-tree is even smaller than a binary tree structure for slicing floorplan which has O(n! 2/sup 5n-3//n/sup 1.5/) combinations. Given an O-tree, it takes only linear time to construct the placement and its constraint graph. We have developed a deterministic floorplanning algorithm utilizing the structure of O-tree. Empirical results on MCNC benchmarks show promising performance with average 16% improvement in wire length, and 1% less in dead space over previous CPU-intensive cluster refinement method.
388 citations
22 Jun 2001
TL;DR: The geometric relation among modules is transparent not only to the TCG representation but also to its operations, facilitating the convergence to a desired solution, and makes TCG an effective and flexible representation for handling the general floorplan/placement design problems with various constraints.
Abstract: In this paper, we propose a transitive closure graph-based representation for general floorplans, called TCG, and show its superior properties. TCG combines the advantages of popular representations such as sequence pair, BSG, and B*-tree. Like sequence pair and BSG, but unlike O-tree, B*-tree, and CBL, TCG is P-admissible. Like B*-tree, but unlike sequence pair, BSG, O-tree, and CBL, TCG does not need to construct additional constraint graphs for the cost evaluation during packing, implying faster runtime. Further, TCG supports incremental update during operations and keeps the information of boundary modules as well as the shapes and the relative positions of modules in the representation. More importantly, the geometric relation among modules is transparent not only to the TCG representation but also to its operations, facilitating the convergence to a desired solution. All these properties make TCG an effective and flexible representation for handling the general floorplan/placement design problems with various constraints. Experimental results show the promise of TCG.
231 citations
Additional excerpts
...TCG (Transitive Closure Graph) and TCG-S having transparent geometric relations among the modules can support incremental update for cost evaluation....
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...BSG [6] n!C(n2, n) O(nlgn) O(nlgn) General Medium TCG [7] O((n!)2) O(n2) O(n2) General Medium TCG-S [8] O((n!)2) O(nlgn) O(n2) General Medium Q-Seq [14] F(n) O(n) 3nlg3n General Low...
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