An Analytical Charge Model for Double-Gate Tunnel FETs
TL;DR: In this article, an analytical charge model for double gate (DG) tunnel FETs was proposed, where the TFET was split into a series combination of a gated tunnel diode and a DG MOSFET.
Abstract: An analytical charge model for double gate (DG) tunnel FETs (TFETs) is proposed. By splitting the TFET into a series combination of a gated tunnel diode and a DG MOSFET, we solved the Poisson equation with matching boundary conditions to obtain a surface potential model for the DG TFET. Based on that, the source depletion charge and the mobile channel charge are derived. Comparisons between the proposed model and TCAD simulations show good agreements and suggest a 100/0 drain/source channel inversion charge partition. Terminal capacitances calculated based on the proposed charge model are also evaluated and show good agreement with TCAD simulations.
Citations
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TL;DR: In this article, the impact of interface traps, both donor and acceptor interface charges, present at the Si/SiO2 interface, on analog/RF performance and linearity distortion analysis of heterogeneous-gate-dielectric gate-all-around tunnel FET (HD-GAA-TFET) was investigated.
Abstract: In this paper, we have investigated device reliability by studying the impact of interface traps, both donor (positive interface charges) and acceptor (negative interface charges), present at the Si/SiO2 interface, on analog/RF performance and linearity distortion analysis of heterogeneous-gate-dielectric gate-all-around tunnel FET (HD-GAA-TFET), which is used to enhance the tunneling current of TFET. Various figures of merit such as cutoff frequency $f_{{T}}$ , maximum oscillation frequency $f_{\max}$ , transconductance frequency product, higher order transconductance coefficients $({g}_{{m}1}, {g}_{{m}3})$ , VIP2, VIP3, IIP3, IMD3, zero crossover point, and 1-dB compression point have been investigated, and the results obtained are simultaneously compared with a gate-all-around TFET (GAA-TFET). Simulation results indicate that HD-GAA-TFET is more immune toward the interface trap charges present at the Si/SiO2 interface than the GAA TFET and hence can act as a better candidate for low power switching applications. All simulations have been done on an ATLAS device simulator.
167 citations
Cites methods from "An Analytical Charge Model for Doub..."
...Abundant techniques have been explored for resolving this issue such as using a smaller band gap material in the source region such as germanium [1], hetero gate dielectric TFET [2], double gate architecture [3], gate to source overlap [4], gate to drain underlap [5], dual material gate [6], n-pocket doping...
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TL;DR: In this paper, a 2D analytic potential model for double-gate (DG) tunnel field effect transistors (TFETs) by solving the 2D Poisson's equation is presented.
Abstract: This paper presents a 2-D analytic potential model for double-gate (DG) tunnel field effect transistors (TFETs) by solving the 2-D Poisson's equation. From the potential profile, the electric field is derived and then the drain current expression is extracted by analytically integrating the band-to-band tunneling generation rate over the tunneling region. The model well predicts the potential, subthreshold swing (SS), and transfer and output characteristics of DG TFETs. We analyze the dependence of the tunneling current on the device parameters by varying the gate oxide dielectric constant, gate oxide thickness, body thickness, channel length and channel material and also demonstrate its agreement with TCAD simulation results. The SS which describes the switching behavior of TFETs, is derived from the current expression. The comparisons show that the SS of our model well coincides with that of simulations.
132 citations
TL;DR: In this article, a simple analytic model based on the Kane-Sze formula is used to describe the currentvoltage characteristics of tunnel field effect transistors (TFETs), including the decrease in subthreshold swing with drain current and the superlinear onset of the output characteristic.
Abstract: A simple analytic model based on the Kane–Sze formula is used to describe the current–voltage characteristics of tunnel field-effect transistors (TFETs). This model captures the unique features of the TFET including the decrease in subthreshold swing with drain current and the superlinear onset of the output characteristic. The model also captures the ambipolar current characteristic at negative gate–source bias and the negative differential resistance for negative drain–source biases. A simple empirical capacitance model is also included to enable circuit simulation. The model has fairly general validity and is not specific to a particular TFET geometry. Good agreement is shown with published atomistic simulations of an InAs double-gate TFET with gate perpendicular to the tunnel junction and with numerical simulations of a broken-gap AlGaSb/InAs TFET with gate in parallel with the tunnel junction.
90 citations
Cites background or methods from "An Analytical Charge Model for Doub..."
...Quite a few compact analytic models for the TFET have been developed [4–14]....
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...[4–9] employ a semianalytical solution of Poisson’s equation in the channel region to model the channel charge [4] or to obtain the current–voltage characteristics [5–9]....
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...These reports focus on particular TFET gate configurations, single-gate (SG) [5–7], double-gate (DG) [4,8,9,11], or gate-all-around [10], or on specific aspects of the transport, such as the output characteristic at small drain biases [12,13]....
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TL;DR: In this paper, an ideal drain current model neglecting the channel transport is developed, which captures the interband tunneling characteristics, describes their geometry dependences, and is suitable for DG TFETs with limited drivability.
Abstract: SPICE modeling of double-gate (DG) tunnel FETs (TFETs) including channel transports is reported. An ideal drain current model neglecting the channel transport is developed first. It captures the interband tunneling characteristics, describes their geometry dependences, and is suitable for DG TFETs with limited drivability. The ideal current model and previously proposed charge model are then extended to include the channel transports. One way to model the transport is appending a DG MOSFET in series with the ideal TFET model. The dependences of TFETs current and terminal charges on channel transports are reproduced. Another way by inserting a resistance at the TFET source side is also proposed with reduced simulation time.
76 citations
Cites background or methods from "An Analytical Charge Model for Doub..."
...With the surface potential solutions in region III, the electrostatic potential expressions in regions I and II are derived [10]....
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...2(a): source junction region (I), channel junction region (II), and channel transport region (III) [10]....
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...The terminal charge is calculated following the same way as in [10]....
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...To reproduce the exponential dependence in the TFET output characteristics and the terminal capacitance properties, it is necessary to consider the charges in the region III [10]....
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...TFET current and capacitance modeling have been reported afterward [5]–[10]....
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TL;DR: In this paper, an analytical model of the channel surface potential in the tunnel field effect transistors (TFETs) is established and verified, and the transition point corresponding to the switching between the two operating regimes is also analyzed quantitatively.
Abstract: In this paper, an analytical model of the channel surface potential in the tunnel field effect transistors (TFETs) is established and verified. The dual-modulation effects in TFETs that the surface potential of the channel is alternatively controlled by the gate bias and drain bias in different operating regimes are emphasized and studied. The transition point corresponding to the switching between the two operating regimes is also analyzed quantitatively. For the first time, a closed-form analytical model of the surface potential in TFETs, including the impacts of both the gate voltage and drain voltage is proposed. Furthermore, a compact current model of the TFET-based on the derived surface potential expression is given. The model predicted tunneling current agree well with the TCAD simulation results in all operating regions of TFETs, which will be helpful for the circuit properties simulation of the TFET.
76 citations
Cites methods from "An Analytical Charge Model for Doub..."
...Several analytical models of the TFET have been reported [8], [9]....
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References
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TL;DR: In this paper, a 70-nm n-channel tunneling field effect transistor (TFET) with sub-threshold swing (SS) of 52.8 mV/dec at room temperature was demonstrated.
Abstract: We have demonstrated a 70-nm n-channel tunneling field-effect transistor (TFET) which has a subthreshold swing (SS) of 52.8 mV/dec at room temperature. It is the first experimental result that shows a sub-60-mV/dec SS in the silicon-based TFETs. Based on simulation results, the gate oxide and silicon-on-insulator layer thicknesses were scaled down to 2 and 70 nm, respectively. However, the ON/ OFF current ratio of the TFET was still lower than that of the MOSFET. In order to increase the on current further, the following approaches can be considered: reduction of effective gate oxide thickness, increase in the steepness of the gradient of the source to channel doping profile, and utilization of a lower bandgap channel material
1,583 citations
"An Analytical Charge Model for Doub..." refers background in this paper
...Higher order corrections are necessary for TFETs with tunneling current around or larger than several tens of μA/μm....
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...For practical TFETs with ON-state currents up to the order of a few μA/μm [3], [4] (much smaller than the DD current of a DG MOSFET with the same geometry parameters and at the same biasing voltages), TCAD simulations [18] show that the perturbation corrections are not significant and the aforementioned zero-order solutions of electrostatic potential and tunneling current are reasonably accurate....
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25 Oct 2010
TL;DR: This review introduces and summarizes progress in the development of the tunnel field- effect transistors (TFETs) including its origin, current experimental and theoretical performance relative to the metal-oxide-semiconductor field-effect transistor (MOSFET), basic current-transport theory, design tradeoffs, and fundamental challenges.
Abstract: Steep subthreshold swing transistors based on interband tunneling are examined toward extending the performance of electronics systems. In particular, this review introduces and summarizes progress in the development of the tunnel field-effect transistors (TFETs) including its origin, current experimental and theoretical performance relative to the metal-oxide-semiconductor field-effect transistor (MOSFET), basic current-transport theory, design tradeoffs, and fundamental challenges. The promise of the TFET is in its ability to provide higher drive current than the MOSFET as supply voltages approach 0.1 V.
1,389 citations
Book•
01 Jan 1986
TL;DR: In this article, the authors present a list of symbols for metal-oxide-silicon systems, including Mos Field-effect transistors, high-field effects, and high-frequency effects.
Abstract: Semiconductor Electronics. Silicon Technology. Metal--Semiconductor Contacts. pn Junctions. Currents in pn Junctions. Bipolar Transistors I: Basic Properties. Bipolar Transistors II: Limitations and Models. Properties of the Metal--Oxide--Silicon System. Mos Field--Effect Transistors I: Physical Effects and Models. Mos Field--Effect Transistors II: High--Field Effects. Answers to Selected Problems. Selected List of Symbols. Index.
1,376 citations
"An Analytical Charge Model for Doub..." refers methods in this paper
...Similar to the full depletion approximation used in the diode modeling [24], it is assumed that the only charge contribution in region II is the intrinsic carrier, and any inversion charge, particularly near x = L2, is ignored....
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TL;DR: In this article, the scaling of fully depleted SOI devices is considered and the concept of controlling horizontal leakage through vertical structures is highlighted, and several structural variations of conventional SOI structures are discussed in terms of a natural length scale to guide the design.
Abstract: Scaling the Si MOSFET is reconsidered. Requirements on subthreshold leakage control force conventional scaling to use high doping as the device dimension penetrates into the deep-submicrometer regime, leading to an undesirably large junction capacitance and degraded mobility. By studying the scaling of fully depleted SOI devices, the important concept of controlling horizontal leakage through vertical structures is highlighted. Several structural variations of conventional SOI structures are discussed in terms of a natural length scale to guide the design. The concept of vertical doping engineering can also be realized in bulk Si to obtain good subthreshold characteristics without large junction capacitance or heavy channel doping. >
921 citations
Additional excerpts
...in which λII = √ εsitsitox/(2εox) is the natural length of the DG MOSFET [21]....
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TL;DR: In this article, the short channel effect in fully depleted silicon-on-insulator MOSFETs has been studied by a two-dimensional analytical model and by computer simulation, and it is found that the vertical field through the depleted film strongly influences the lateral field across the source and drain regions.
Abstract: The short-channel effect in fully depleted silicon-on-insulator MOSFETs has been studied by a two-dimensional analytical model and by computer simulation. The calculated values agree well with the simulation results. It is found that the vertical field through the depleted film strongly influences the lateral field across the source and drain regions. The short-channel effect can be significantly reduced by decreasing the silicon film thickness. >
789 citations
"An Analytical Charge Model for Doub..." refers methods in this paper
..., using a second-order polynomial to describe the potential profile normal to the channel direction) is proved useful to derive analytical solutions of 2-D Poisson equations in device modeling [20]–[22], and it also applies here to regions I and II....
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